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Analysis of Parallel SOC Architectural Characteristics for Accelerating Face Identification

Sprang, Ralph (2012) Analysis of Parallel SOC Architectural Characteristics for Accelerating Face Identification. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

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Growing worldwide concerns about terrorism have increased interest in rapidly and accurately identifying individuals such as potential terrorists. The ability to quickly screen an individual against the more than one million entries on the Terrorist Watch List using face identification could significantly improve national security and other security screening applications.
Top accuracy face identification algorithms are not real-time. The top face identification algorithms evaluated in National Institutes of Standards (NIST) testing achieve 95% or greater identification accuracy but require several minutes to complete identification on a 1,196 member gallery set of 100 kilopixel resolution images. Recent testing shows that face identification algorithms are significantly slower for current NIST test sets with a 14,365 member gallery set of 4 megapixel images. Significant performance improvement is needed to match a one million member gallery set.
The International Technology Roadmap for Semiconductors projects Systems on a Chip with more than one thousand processors will be available within ten years. However, it’s not clear how face identification algorithms can use these massively parallel SOCs to improve performance or which architectural characteristics are important for these algorithms.
This research specifies key architectural characteristics for a massively parallel SOC to enable real-time face identification. A set of face identification benchmarks has been created to guide this research and includes small and large image data sets. This research contributes a method to explore the SOC design space to evaluate the final SOC performance. Specifically, this research is focused on the impact of processor instruction set architecture performance, the external memory bandwidth, the quantity of processing cores, the on-chip communication network, and the mapping of the face identification benchmarks.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairCain, James Tjtc@pitt.eduJTC
Committee CoChairHoare, Raymond
Committee MemberJones, Alex Kakjones@pitt.eduAKJONES
Committee MemberLevitan, Stephen Plevitan@pitt.eduLEVITAN
Committee MemberMickle, Marlin Hmickle@pitt.eduMICKLE
Committee MemberMooney, Mark Pmpm4@pitt.eduMPM4
Date: 26 September 2012
Date Type: Publication
Defense Date: 4 April 2012
Approval Date: 26 September 2012
Submission Date: 7 June 2012
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 206
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical Engineering
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: Face Recognition, Systems on a Chip, Computer architecture, Biometric identification, Parallel processing, microprocessor
Date Deposited: 26 Sep 2012 15:36
Last Modified: 15 Nov 2016 13:58


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