C-AMTE: A location mechanism for flexible cache management in chip multiprocessors

Hammoud, M and Cho, S and Melhem, R (2011) C-AMTE: A location mechanism for flexible cache management in chip multiprocessors. UNSPECIFIED. UNSPECIFIED.

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Abstract

This paper describes Constrained Associative-Mapping-of-Tracking-Entries (C-AMTE), a scalable mechanism to facilitate flexible and efficient distributed cache management in large-scale chip multiprocessors (CMPs). C-AMTE enables fast locating of cache blocks in CMP cache schemes that employ one-to-one or one-to-many associative mappings. C-AMTE stores in per-core data structures tracking entries to avoid on-chip interconnect traffic outburst or long distance directory lookups. Simulation results using a full system simulator demonstrate that C-AMTE achieves improvement in cache access latency by up to 34.4%, close to that of a perfect location strategy. © 2010 Elsevier Inc. All rights reserved.

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Details

Item Type:	Monograph (UNSPECIFIED)
Status:	Published
Creators/Authors:	Creators Email Pitt Username ORCID Hammoud, M Cho, S Melhem, R melhem@cs.pitt.edu MELHEM
Date:	1 June 2011
Date Type:	Publication
Access Restriction:	No restriction; Release the ETD for access worldwide immediately.
Journal or Publication Title:	Journal of Parallel and Distributed Computing
Volume:	71
Number:	6
Page Range:	889 - 896
DOI or Unique Handle:	10.1016/j.jpdc.2010.11.009
Institution:	University of Pittsburgh
Department:	Computer Science
Schools and Programs:	Dietrich School of Arts and Sciences > Computer Science Dietrich School of Arts and Sciences > Computer Science > Computer Science Technical Reports
Refereed:	No
ISSN:	0743-7315
Related URLs:	http://dx.doi.org/10.1016/j.jpdc.2010.11.009
University of Pittsburgh Series:	Computer Science Technical Reports
Other ID:	CS TR 09 166
Date Deposited:	12 Mar 2013 18:14
Last Modified:	02 Feb 2019 15:55
URI:	http://d-scholarship.pitt.edu/id/eprint/17755

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