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Dynamic cache clustering for chip multiprocessors

Hammoud, M and Cho, S and Melhem, R (2009) Dynamic cache clustering for chip multiprocessors. UNSPECIFIED. UNSPECIFIED.

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This paper proposes DCC (Dynamic Cache Clustering), a novel distributed cache management scheme for large-scale chip multiprocessors. Using DCC, a per-core cache cluster is comprised of a number of L2 cache banks and cache clusters are constructed, expanded, and contracted dynamically to match each core's cache demand. The basic trade-offs of varying the on-chip cache clusters are average L2 access latency and L2 miss rate. DCC uniquely and efficiently optimizes both metrics and continuously tracks a near-optimal cache organization from many possible configurations. Simulation results using a full-system simulator demonstrate that DCC outperforms alternative L2 cache designs. Copyright 2009 ACM.


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Item Type: Monograph (UNSPECIFIED)
Status: Published
CreatorsEmailPitt UsernameORCID
Hammoud, M
Cho, S
Melhem, Rmelhem@cs.pitt.eduMELHEM
Date: 24 November 2009
Date Type: Publication
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Journal or Publication Title: Proceedings of the International Conference on Supercomputing
Page Range: 56 - 67
Event Type: Conference
DOI or Unique Handle: 10.1145/1542275.1542289
Institution: University of Pittsburgh
Department: Computer Science
Schools and Programs: Dietrich School of Arts and Sciences > Computer Science
Dietrich School of Arts and Sciences > Computer Science > Computer Science Technical Reports
Refereed: No
ISBN: 9781605584980
University of Pittsburgh Series: Computer Science Technical Reports
Other ID: CS TR 08 162
Date Deposited: 12 Mar 2013 18:10
Last Modified: 02 Feb 2019 15:56


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