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Software-Oriented Data Access Characterization for Chip Multiprocessor Architecture Optimizations

Li, Yong (2014) Software-Oriented Data Access Characterization for Chip Multiprocessor Architecture Optimizations. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

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The integration of an increasing amount of on-chip hardware in Chip-Multiprocessors (CMPs) poses a challenge of efficiently utilizing the on-chip resources to maximize performance. Prior research proposals largely rely on additional hardware support to achieve desirable tradeoffs. However, these purely hardware-oriented mechanisms typically result in more generic but less efficient approaches. A new trend is designing adaptive systems by exploiting and leveraging application-level information. In this work a wide range of applications are analyzed and remarkable data access behaviors/patterns are recognized to be useful for architectural and system optimizations. In particular, this dissertation work introduces software-based techniques that can be used to extract data access characteristics for cross-layer optimizations on performance and scalability. The collected information is utilized to guide cache data placement, network configuration, coherence operations, address translation, memory configuration, etc. In particular, an approach is proposed to classify data blocks into different categories to optimize an on-chip coherent cache organization. For applications with compile-time deterministic data access localities, a compiler technique
is proposed to determine data partitions that guide the last level cache data placement and communication patterns for network configuration. A page-level data classification is also demonstrated to improve address translation performance. The successful utilization of data access characteristics on traditional CMP architectures demonstrates that the proposed approach is promising and generic and can be potentially applied to future CMP architectures with emerging technologies such as the Spin-transfer torque RAM (STT-RAM).


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Li, Yongyol26@pitt.eduYOL26
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairJones, Alexakjones@pitt.eduAKJONES
Committee CoChairMelhem, Ramimelhem@cs.pitt.eduMELHEM
Committee MemberLi, Haihal66@pitt.eduHAL66
Committee MemberChen, Yiranyic52@pitt.eduYIC52
Committee MemberMao, Zhi-Hongzhm4@pitt.eduZHM4
Date: 29 January 2014
Date Type: Publication
Defense Date: 29 October 2013
Approval Date: 29 January 2014
Submission Date: 2 December 2013
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 165
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Computer Engineering
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: Data Classification, Data Access Pattern, Chip Multiprocessors, Compiler, Caches, TLBs
Date Deposited: 29 Jan 2014 18:28
Last Modified: 15 Nov 2016 14:16


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