Link to the University of Pittsburgh Homepage
Link to the University Library System Homepage Link to the Contact Us Form

Improving the Reliability of Microprocessors under BTI and TDDB Degradations

Li, Lin (2014) Improving the Reliability of Microprocessors under BTI and TDDB Degradations. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

PDF (Lin Li's PhD Dissertation)
Submitted Version

Download (1MB) | Preview


Reliability is a fundamental challenge for current and future microprocessors with advanced nanoscale technologies. With smaller gates, thinner dielectric and higher temperature microprocessors are vulnerable under aging mechanisms such as Bias Temperature Instability (BTI) and Temperature Dependent Dielectric Breakdown (TDDB). Under continuous stress both parametric and functional errors occur, resulting compromised microprocessor lifetime. In this thesis, based on the thorough study on BTI and TDDB mechanisms, solutions are proposed to mitigating the aging processes on memory based and random logic structures in modern out-of-order microprocessors.

A large area of processor core is occupied by memory based structure that is vulnerable to BTI induced errors. The problem is exacerbated when PBTI degradation in NMOS is as severe as NBTI in PMOS in high-k metal gate technology. Hence a novel design is proposed to recover 4 internal gates within a SRAM cell simultaneously to mitigate both NBTI and PBTI effects. This technique is applied to both the L2 cache banks and the busy function units with storage cells in out-of-order pipeline in two different ways. For the L2 cache banks, redundant cache bank is added exclusively for proactive recovery rotation. For the critical and busy function units in out-of-order pipelines, idle cycles are exploited at per-buffer-entry level.

Different from memory based structures, combinational logic structures such as function units in execution stage can not use low overhead redundancy to tolerate errors due to their irregular structure. A design framework that aims to improve the reliability of the vulnerable functional units of a processor core is designed and implemented. The approach is designing a generic function unit (GFU) that can be reconfigured to replace a particular functional unit (FU) while it is being recovered for improved lifetime. Although flexible, the GFU is slower than the original target FUs. So GFU is carefully designed so as to minimize the performance loss when it is in-use. More schemes are also designed to avoid using the GFU on performance critical paths of a program execution.


Social Networking:
Share |


Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Li, Linlil53@pitt.eduLIL53
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairYang, Junjuy9@pitt.eduJUY9
Committee CoChairZhang, Youtaozhangyt@cs.pitt.eduYOUTAO
Committee MemberLevitan, Stevelevitan@pitt.eduLEVITAN
Committee MemberCho, Sangyeuncho@cs.pitt.eduSANGYEUN
Committee MemberWang, Jingtaojingtaow@cs.pitt.eduJINGTAOW
Date: 16 June 2014
Date Type: Publication
Defense Date: 18 October 2013
Approval Date: 16 June 2014
Submission Date: 27 March 2014
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 123
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Computer Engineering
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: computer processor, reliability, aging, BTI, TDDB, reconfigurable function unit
Date Deposited: 16 Jun 2014 19:15
Last Modified: 15 Nov 2016 14:18


Monthly Views for the past 3 years

Plum Analytics

Actions (login required)

View Item View Item