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Compression architecture for bit-write reduction in non-volatile memory technologies

Dgien, David (2014) Compression architecture for bit-write reduction in non-volatile memory technologies. Master's Thesis, University of Pittsburgh. (Unpublished)

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In this thesis we explore a novel method for improving the performance and lifetime of non-volatile memory technologies. As the development of new DRAM technology reaches physical scaling limits, research into new non-volatile memory technologies has advanced in search of a possible replacement. However, many of these new technologies have inherent problems such as low endurance, long latency, or high dynamic energy. This thesis proposes a simple compression-based technique to improve the performance of write operations in non-volatile memories by reducing the number of bit-writes performed during write accesses. The proposed architecture, which is integrated into the memory controller, relies on a compression engine to reduce the size of each word before it is written to the memory array. It then employs a comparator to determine which bits require write operations. By reducing the number of bit-writes, these elements are capable of reducing the energy consumed, improving throughput, and increasing endurance of non-volatile memories. We examine two different compression methods for compressing each word in our architecture. First, we explore Frequent Value Compression (FVC), which maintains a dictionary of the words used most frequently by the application. We also use a Huffman Coding scheme to perform the compression of these most frequent values. Second, we explore Frequent Pattern Compression (FPC), which compresses each word based on a set of patterns. While this method is not capable of reducing the size of each word as well as FVC, it is capable of compressing a greater number of values. Finally, we implement an intra-word wear leveling method that is able to enhance memory endurance by reducing the peak bit-writes per cell. This method conditionally writes compressed words to separate portions of the non-volatile memory word in order to spread writes throughout each word. Trace-based simulations of the SPEC CPU2006 benchmarks show a 20x reduction in raw bit-writes, which corresponds to a 2-3x improvement over the state-of-the-art methods and a 27% reduction in peak cell bit-writes, improving NVM lifetime.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Dgien, Daviddbd12@pitt.eduDBD12
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairMohanram, Kartikkmram@pitt.eduKMRAM
Committee MemberLevitan, Stevenlevitan@pitt.eduLEVITAN
Committee MemberYang, Junjuy9@pitt.eduJUY9
Date: 16 June 2014
Date Type: Publication
Defense Date: 28 March 2014
Approval Date: 16 June 2014
Submission Date: 3 April 2014
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 61
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical Engineering
Degree: MS - Master of Science
Thesis Type: Master's Thesis
Refereed: Yes
Uncontrolled Keywords: Nonvolatile memory, Compression, Phase Change Memory, Spin-Transfer Torque RAM, Resistive RAM, Main Memory
Date Deposited: 16 Jun 2014 17:53
Last Modified: 15 Nov 2016 14:18


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