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Codeword assignment for cell-write reduction in non-volatile memory technologies

Hunter, Nathan Altay (2014) Codeword assignment for cell-write reduction in non-volatile memory technologies. Master's Thesis, University of Pittsburgh. (Unpublished)

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This thesis explores a context-independent limited-weight codeword assignment architecture for cell-write reduction in emerging single-level cell (SLC) and multi-level cell (MLC) non-volatile memories (NVMs). Cell-write reduction in NVMs has many practical benefits, including lower write latency, lower dynamic energy, and enhanced endurance. The proposed architecture, which is integrated into the memory controller, relies on an a priori analysis of memory access patterns and a remapping table to minimize overwrites in NVM cells. The baseline for comparison used for comparing our algorithms is a technique known as data-comparison write (DCW) which performs a cell-wise comparison of the write data before each operation. This reduces cell-writes by allowing only the cells whose value changes to be rewritten. Similarly, Flip-N-Write (FNW), a technique which allows each word written to memory to be optionally inverted, serves as the state-of-the-art technique our schemes outperform. Our first algorithm relies on the different frequencies with which each value is written to memory to perform a frequency-based assignment (FBA) of codewords. Based on a set of training data, the most frequently occurring values are mapped to limited-weight codes (LWC) to reduce the number of bit-writes. Our second algorithm further improves upon FBA by considering the sequence in which values transition to one another to perform a sequence-based assignment (SBA) of codewords. All three methods are then modified to provide similar improvements in multi-level cell (MLC) memories. Since bit-write reduction is distinct from cell-write reduction in MLC, the LWCs are changed for FBA, the algorithm used by SBA to calculate node weights are modified, and a different approach to cell inversion for FNW is considered. Trace-based simulations of the SPEC CPU2006 benchmarks show a 33× reduction in raw bit-writes in SLC and a 28× reduction in raw cell-writes in 2-bit MLC. These correspond to a 19% and 15% improvement over the best state-of-the-art method respectively.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Hunter, Nathan
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairMohanram, Kartikkmram@pitt.eduKMRAM
Committee MemberLevitan, Stevenlevitan@pitt.eduLEVITAN
Committee MemberYang, Junjuy9@pitt.eduJUY9
Date: 19 September 2014
Date Type: Publication
Defense Date: 18 April 2014
Approval Date: 19 September 2014
Submission Date: 30 June 2014
Access Restriction: 5 year -- Restrict access to University of Pittsburgh for a period of 5 years.
Number of Pages: 52
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical Engineering
Degree: MS - Master of Science
Thesis Type: Master's Thesis
Refereed: Yes
Uncontrolled Keywords: Non-volatile memory, Codeword substitution, Phase Change Memory, Spin-Transfer Torque RAM, Resistive RAM, Main Memory
Date Deposited: 19 Sep 2014 16:51
Last Modified: 19 Sep 2019 05:15


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