Link to the University of Pittsburgh Homepage
Link to the University Library System Homepage Link to the Contact Us Form
D-Scholarship @ Pitt Banner and Links to Homepage

Novel Single and Hybrid Finite Field Multipliers over GF(2m) for Emerging Cryptographic Systems

Xie, Jiafeng (2015) Novel Single and Hybrid Finite Field Multipliers over GF(2m) for Emerging Cryptographic Systems. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

[img]
Preview
 PDF
Primary Text
Download (2MB)

Abstract

With the rapid development of economic and technical progress, designers and users of various kinds of ICs and emerging embedded systems like body-embedded chips and wearable devices are increasingly facing security issues. All of these demands from customers push the cryptographic systems to be faster, more efficient, more reliable and safer. On the other hand, multiplier over GF(2m) as the most important part of these emerging cryptographic systems, is expected to be high-throughput, low-complexity, and low-latency. Fortunately, very large scale integration (VLSI) digital signal processing techniques offer great facilities to design efficient multipliers over GF(2m).

This dissertation focuses on designing novel VLSI implementation of high-throughput
low-latency and low-complexity single and hybrid finite field multipliers over GF(2m) for emerging cryptographic systems. Low-latency (latency can be chosen without any restriction) high-speed pentanomial basis multipliers are presented. For the first time, the dissertation also develops three high-throughput digit-serial multipliers based on pentanomials. Then a novel realization of digit-level implementation of multipliers based on redundant basis is introduced. Finally, single and hybrid reordered normal basis bit-level and digit-level high-throughput multipliers are presented. To the authors knowledge, this is the first time ever reported on multipliers with multiple throughput rate choices. All the proposed designs are simple and modular, therefore suitable for VLSI implementation for various emerging cryptographic systems.

Share

Citation/Export:
Social Networking:
Share |

Details

Item Type: University of Pittsburgh ETD
Status: Unpublished
Creators/Authors:
CreatorsEmailPitt UsernameORCID
Xie, Jiafengjix49@pitt.eduJIX49
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairMao, Zhi-Hongzhm4@pitt.eduZHM4
Committee CoChairMeher, Pramodaspkmeher@ntu.edu.sg
Committee MemberChaparro, Luislfch@pitt.eduLFCH
Committee MemberMcDermott, Thomastem42@pitt.eduTEM42
Committee MemberReed, Gregorygfr3@pitt.eduGFR3
Committee MemberSejdić, Ervinesejdic@pitt.eduESEJDIC
Committee MemberSun, Minguidrsun@pitt.eduDRSUN
Date: 28 January 2015
Date Type: Publication
Defense Date: 4 August 2014
Approval Date: 28 January 2015
Submission Date: 7 November 2014
Access Restriction: 3 year -- Restrict access to University of Pittsburgh for a period of 3 years.
Number of Pages: 172
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical Engineering
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: Finite field multiplier, emerging cryptographic systems, high-throughput, VLSI
Date Deposited: 28 Jan 2015 21:05
Last Modified: 28 Jan 2018 06:15
URI: http://d-scholarship.pitt.edu/id/eprint/23475

Metrics

Monthly Views for the past 3 years

Plum Analytics

Actions (login required)

View Item View Item