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Architectural Techniques for Multi-Level Cell Phase Change Memory Based Main Memory

Jiang, Lei (2015) Architectural Techniques for Multi-Level Cell Phase Change Memory Based Main Memory. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

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Phase change memory (PCM) recently has emerged as a promising technology to meet the fast growing demand for large capacity main memory in modern computing systems. Multi-level cell (MLC) PCM storing multiple bits in a single cell offers high density with low per-byte fabrication cost. However, PCM suffers from long write latency, short cell endurance, limited write throughput and high peak power, which makes it challenging to be integrated in the memory hierarchy.

To address the long write latency, I propose write truncation to reduce the number of write iterations with the assistance of an extra error correction code (ECC). I also propose form switch (FS) to reduce the storage overhead of the ECC. By storing highly compressible lines in single level cell (SLC) form, FS improves read latency as well.

To attack the short cell endurance and large peak power, I propose elastic RESET (ER) to construct triple-level cell PCM. By reducing RESET energy, ER significantly reduces peak power and prolongs PCM lifetime.

To improve the write concurrency, I propose fine-grained write power budgeting (FPB) observing a global power budget and regulates power across write iterations according to the step-down power demand of each iteration. A global charge pump is also integrated onto a DIMM to boost power for hot PCM chips while staying within the global power budget.

To further reduce the peak power, I propose intra-write RESET scheduling distributing cell RESET initializations in the whole write operation duration, so that the on-chip charge pump size can also be reduced.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Jiang, Leilej16@pitt.eduLEJ16
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairYang, Junjuy9@pitt.eduJUY9
Committee CoChairZhang, Youtaozhangyt@cs.pitt.eduYOUTAO
Committee MemberChilders, Brucechilders@cs.pitt.eduCHILDERS
Committee MemberLevitan, Steven levitan@pitt.eduLEVITAN
Committee MemberPelechrinis, Konstantinoskpele@pitt.eduKPELE
Date: 28 January 2015
Date Type: Publication
Defense Date: 17 October 2014
Approval Date: 28 January 2015
Submission Date: 14 November 2014
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 139
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Computer Engineering
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: Phase Change Memory, Multi-level Cell, Charge Pump, Error Correcting Code, Memory Hierarchy, Main Memory
Date Deposited: 28 Jan 2015 20:36
Last Modified: 15 Nov 2016 14:25


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