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Emerging Run-Time Reconfigurable FPGA and CAD Tools

Chen, Yi-Chung (2015) Emerging Run-Time Reconfigurable FPGA and CAD Tools. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

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Field-programmable gate array (FPGA) is a post fabrication reconfigurable device to accelerate domain specific computing systems. It offers offer high operation speed and low power consumption. However, the design flexibility and performance of FPGAs are severely constrained by the costly on-chip memories, e.g. static random access memory (SRAM) and FLASH memory. The objective of my dissertation is to explore the opportunity and enable the use of the emerging resistance random access memory (ReRAM) in FPGA design.
The emerging ReRAM technology features high storage density, low access power consumption, and CMOS compatibility, making it a promising candidate for FPGA implementation. In particular, ReRAM has advantages of the fast access and nonvolatility, enabling the on-chip storage and access of configuration data. In this dissertation, I first propose a novel three-dimensional stacking scheme, namely, high-density interleaved memory (HIM). The structure improves the density of ReRAM meanwhile effectively reducing the signal interference induced by sneak paths in crossbar arrays. To further enhance the access speed and design reliability, a fast sensing circuit is also presented which includes a new sense amplifier scheme and reference cell configuration.
The proposed ReRAM FPGA leverages a similar architecture as conventional SRAM based FPGAs but utilizes ReRAM technology in all component designs. First, HIM is used to implement look-up table (LUT) and block random access memories (BRAMs) for func- tionality process. Second, a 2R1T, two ReRAM cells and one transistor, nonvolatile switch design is applied to construct connection blocks (CBs) and switch blocks (SBs) for signal transition. Furthermore, unified BRAM (uBRAM) based on the current BRAM architecture
is introduced, offering both configuration and temporary data storage. The uBRAMs provides extremely high density effectively and enlarges the FPGA capacity, potentially saving multiple contexts of configuration. The fast configuration scheme from uBRAM to logic and routing components also makes fast run-time partial reconfiguration (PR) much easier, improving the flexibility and performance of the entire FPGA system.
Finally, modern place and route tools are designed for homogeneous fabric of FPGA. The PR feature, however, requires the support of heterogeneous logic modules in order to differentiate PR modules from static ones and therefore maintain the signal integration. The existing approaches still reply on designers’ manual effort, which significantly prolongs design time and lowers design efficiency. In this dissertation, I integrate PR support into VPR – an academic place and route tool by introducing a B*-tree modular placer (BMP) and PR-aware router. As such, users are able to explore new architectures or map PR applications to a variety of FPGAs. More importantly, this enhanced feature can also support fast design automation, e.g. mapping IP core, loading pre-synthesizing logic modules, etc.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Chen, Yi-Chungyic63@pitt.eduYIC63
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairLi, Hai (Helen)HAL66@pitt.eduHAL66
Committee MemberZhang,
Committee MemberMohanram, Kartikkmram@pitt.eduKMRAM
Committee MemberJones, Alex K.akjones@pitt.eduAKJONES
Committee MemberYang, Junjuy9@pitt.eduJUY9
Committee MemberChen, Yiranyic52@pitt.eduYIC52
Date: 28 January 2015
Date Type: Publication
Defense Date: 24 October 2014
Approval Date: 28 January 2015
Submission Date: 17 November 2014
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 129
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical and Computer Engineering
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: ReRAM, FPGA, RRAM, CAD, Place and Route, uBRAM, Modular place, PR-aware routing
Date Deposited: 28 Jan 2015 21:55
Last Modified: 15 Nov 2016 14:25


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