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Error Characterization and Correction Techniques for Reliable STT-RAM Designs

Wen, Wujie (2015) Error Characterization and Correction Techniques for Reliable STT-RAM Designs. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

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The concerns on the continuous scaling of mainstream memory technologies have motivated tremendous investment to emerging memories. Being a promising candidate, spin-transfer torque random access memory (STT-RAM) offers nanosecond access time comparable to SRAM, high integration density close to DRAM, non-volatility as Flash memory, and good scalability. It is well positioned as the replacement of SRAM and DRAM for on-chip cache and main memory applications. However, reliability issue continues being one of the major challenges in STT-RAM memory designs due to the process variations and unique thermal fluctuations, i.e., the stochastic resistance switching property of magnetic devices.

In this dissertation, I decoupled the reliability issues as following three-folds: First, the characterization of STT-RAM operation errors often require expensive Monte-Carlo runs with hybrid magnetic-CMOS simulation steps, making it impracticable for architects and system designs; Second, the state of the art does not have sufficiently understanding on the unique reliability issue of STT-RAM, and conventional error correction codes (ECCs) cannot efficiently handle such errors; Third, while the information density of STT-RAM can be boosted by multi-level cell (MLC) design, the more prominent reliability concerns and the complicated access mechanism greatly limit its applications in memory subsystems.

Thus, I present a novel through solution set to both characterize and tackle the above reliability challenges in STT-RAM designs. In the first part of the dissertation, I introduce a new characterization method that can accurately and efficiently capture the multi-variable design metrics of STT-RAM cells; Second, a novel ECC scheme, namely, content-dependent ECC (CD-ECC), is developed to combat the characterized asymmetric errors of STT-RAM at 0->1 and 1->0 bit flipping's; Third, I present a circuit-architecture design, namely state-restricted multi-level cell (SR-MLC) STT-RAM design, which simultaneously achieves high information density, good storage reliability and fast write speed, making MLC STT-RAM accessible for system designers under current technology node. Finally, I conclude that efficient robust (or ECC) designs for STT-RAM require a deep holistic understanding on three different levels-device, circuit and architecture. Innovative ECC schemes and their architectural applications, still deserve serious research and investigation in the near future.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Wen, Wujiewuw2@pitt.eduWUW2
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairChen, Yiranyic52@pitt.eduYIC52
Committee MemberMelhem, Ramimelhem@cs.pitt.eduMELHEM
Committee MemberLi, HaiHAL66@pitt.eduHAL66
Committee MemberSejdić, Ervinesejdic@pitt.eduESEJDIC
Committee MemberMao, Zhi-Hongzhm4@pitt.eduZHM4
Date: 11 September 2015
Date Type: Publication
Defense Date: 1 June 2015
Approval Date: 11 September 2015
Submission Date: 4 June 2015
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 113
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical Engineering
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: STT-RAM, Reliability, Error Characterization, Error Correction, Asymmetry, Multi-level Cell
Date Deposited: 11 Sep 2015 17:20
Last Modified: 15 Nov 2016 14:28


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