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A Self-Organizing Wireless Sensor Network and Distributed Computing Engine for Commodity and Future Palmtop Computers

Xu, Haifeng (2015) A Self-Organizing Wireless Sensor Network and Distributed Computing Engine for Commodity and Future Palmtop Computers. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

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The embedded class processors found in commodity palmtop computers continue to become increasingly capable while retaining an energy-efficient footprint. Palmtop computers themselves, including smartphones and tablets, provide a small form factor system integrating wireless communication and non-volatile storage with these energy-efficient processors. Also, various wireless connectivity functions on mobile devices provide new opportunities in designing more flexible, smarter wireless sensor networks (WSNs), and utilizing the computation power in a way we could never imagine before. In this dissertation, I present a WSN concept for current and future generation tablet devices. My contributions include developments at the system level, architecture level, and collaborative design between different layers of the system. At the system level, I developed Ocelot, a grid-like computing environment for palmtop computers in place of traditional workstation or server class machines to compute highly parallel light to medium-weight tasks in an energy efficient manner. Additionally, I developed Lynx, a self-organizing wireless sensor network, which is a further step taken in exploiting the potential of palmtop computers. At the architecture level, to increase the storage capacity of future palmtop computers, I explore the use of a new storage class magnetic memory, Racetrack Memory (RM), throughout the memory hierarchy. Thus, I developed FusedCache, a naturally inclusive, dual-level private cache design for RM that provides fast uniform access at one level, and non-uniform access at the next, which allows RM to be effective as close to the processor as an L1 cache. For higher levels of the memory hierarchy such as the last level cache, I propose a Multilane Racetrack Cache (MRC), an RM last level cache design utilizing lightweight compression combined with independent shifting. MRCs allow cache lines mapped to the same Racetrack structure to be accessed in parallel when compressed, mitigating potential shifting stalls in an RM cache. Finally, leveraging the lightweight compression from MRC and the need for efficient communication in Lynx, I present a cross-level design combining memory-level lightweight compression with network-level packet transfer, together with a technique called Source-Aware Layout Reorganization (SALR) to increase the compressibility of sensor data.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Xu, Haifenghax6@pitt.eduHAX6
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairJones, Alex K.akjones@pitt.eduAKJONES
Committee MemberLi, HAL66
Committee MemberChen, Yiranyic52@pitt.eduYIC52
Committee MemberSejdić, Ervinesejdic@pitt.eduESEJDIC
Committee MemberBilec, Melissa M.mbilec@pitt.eduMBILEC
Date: 11 September 2015
Date Type: Publication
Defense Date: 25 June 2015
Approval Date: 11 September 2015
Submission Date: 14 July 2015
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 141
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical Engineering
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: Wireless sensor networks, distributed computing, palmtop,
Date Deposited: 11 Sep 2015 17:26
Last Modified: 15 Nov 2016 14:29


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