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A Statistical STT-RAM Design View and Robust Designs at Scaled Technologies

Zhang, Yaojun and Chen, Yiran (2017) A Statistical STT-RAM Design View and Robust Designs at Scaled Technologies. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

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Rapidly increased demands for memory in electronic industry and the significant technical scaling challenges of all conventional memory technologies motivated the researches on the next generation memory technology. As one promising candidate, spin-transfer torque random access memory (STT-RAM) features fast access time, high density, non-volatility, and good CMOS process compatibility. In recent years, many researches have been conducted to improve the storage density and enhance the scalability of STT-RAM, such as reducing the write current and switching time of magnetic tunneling junction (MTJ) devices. In parallel with these efforts, the continuous increasing of tunnel magneto-resistance(TMR) ratio of the MTJ inspires the development of multi-level cell (MLC) STT-RAM, which allows multiple data bits be stored in a single memory cell. Two types of MLC STT-RAM cells, namely, parallel MLC and series MLC, were also proposed. However, like all other nanoscale devices, the performance and reliability of STT-RAM cells are severely affected by process variations, intrinsic device operating uncertainties and environmental fluctuations. The storage margin of a MLC STT-RAM cell, i.e., the distinction between the lowest and highest resistance states, is partitioned into multiple segments for multi-level data representation. As a result, the performance and reliability of MLC STT-RAM cells become more sensitive to the MOS and MTJ device variations and the thermal-induced randomness of MTJ switching. In this work, we systematically analyze the impacts of CMOS and MTJ process variations, MTJ resistance switching randomness that induced by intrinsic thermal fluctuations, and working temperature changes on STT-RAM cell designs. The STT-RAM cell reliability issues in both read and write operations are first investigated. A combined circuit and magnetic simulation platform is then established to quantitatively study the persistent and non-persistent errors in STT-RAM cell operations. Then, we analyzed the extension of STT-RAM cell behaviors from SLC (single-level- cell) to MLC (multi-level- cell). On top of that, we also discuss the optimal device parameters of the MLC MTJ for the minimization of the operation error rate of the MLC STT-RAM cells from statistical design perspective. Our simulation results show that under the current available technology, series MLC STT-RAM demonstrates overwhelming benefits in the read and write reliability compared to parallel MLC STT-RAM and could potentially satisfy the requirement of commercial practices. Finally, with the detail analysis study of STT-RAM cells, we proposed several error reduction design, such as ADAMS structure, and FA-STT structure.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Zhang, Yaojunyaz24@pitt.eduyaz24
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairChen,
Committee MemberLi,
Committee MemberLi,
Committee MemberSejdic,
Committee MemberSun,
Date: 14 June 2017
Date Type: Publication
Defense Date: 1 November 2016
Approval Date: 14 June 2017
Submission Date: 28 November 2016
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 109
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Computer Engineering
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: STT-RAM Process Variation Reliability Non-volatile Memory
Date Deposited: 14 Jun 2017 18:32
Last Modified: 14 Jun 2017 18:32

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