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Low Energy Solutions for Multi- and Triple-Level Cell Non-Volatile Memories

Alsuwaiyan, Ali (2017) Low Energy Solutions for Multi- and Triple-Level Cell Non-Volatile Memories. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

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Due to the high refresh power and scalability issues of DRAM, non-volatile memories (NVM) such as phase change memory (PCM) and resistive RAM (RRAM) are being actively investigated as viable replacements of DRAM. However, although these NVMs are more scalable than DRAM, they have shortcomings such as higher write energy and lower endurance. Further, the increased capacity of multi- and triple-level cells (MLC/TLC) in these NVM technologies comes at the cost of even higher write energies and lower endurance attributed to the MLC/TLC program-and-verify
(P&V) techniques.

This dissertation makes the following contributions to address the high write energy associated with MLC/TLC NVMs. First, we describe MFNW, a Flip-N-Write encoding that effectively reduces the write energy and improves the endurance of MLC NVMs. MFNW encodes an MLC/TLC word into a number of codewords and selects the one resulting in lowest write energy. Second, we present another encoding solution that is based on perfect knowledge frequent value encoding (FVE). This encoding technique leverages machine learning to cluster a set of general-purpose applications according to their frequency profiles and generates a dedicated offline FVE for every cluster to maximize energy reduction across a broad spectrum of applications. Whereas the proposed encodings are used as an add-on layer on top of the MLC/TLC P&V solutions, the third contribution is a low latency, low energy P&V (L3EP) approach for MLC/TLC PCM. The primary motivation of L^3EP is to fix the problem from its origin by crafting a higher speed programming algorithm. A reduction in write latency implies a reduction in write energy as well as an improvement in cell endurance.

Directions for future research include the integration and evaluation of a software-based hybrid encoding mechanism for MLC/TLC NVMs; this is a page-level encoding that employs a DRAM cache for coding/decoding purposes. The main challenges include how the cache block replacement algorithm can easily access the page-level auxiliary cells to encode the cache block correctly. In summary, this work presents multiple solutions to address major challenges of MLC/TLC NVMs, including write latency, write energy, and cell endurance.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Alsuwaiyan, Aliasa78@pitt.eduasa78
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairMohanram, Kartikkmram@pitt.edukmram
Li, Hai (Helen)
Mao, Zhi-Hongzhm4@pitt.eduzhm4
Miskov-Zivanov, Natasanmzivanov@pitt.edunam66
Zhang, Youtaoyoutao@pitt.eduyoutao
Date: 26 September 2017
Date Type: Publication
Defense Date: 11 May 2017
Approval Date: 26 September 2017
Submission Date: 13 July 2017
Access Restriction: 2 year -- Restrict access to University of Pittsburgh for a period of 2 years.
Number of Pages: 110
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical and Computer Engineering
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: Non-volatile memories Phase change memory Resistive RAM Data encoding Multi-level cell Triple-level cell Write energy Write latency Memory endurance
Date Deposited: 26 Sep 2017 19:55
Last Modified: 26 Sep 2019 05:15


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