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Investigating, Optimizing, and Emulating Candidate Architectures for On-Board Space Processing

Schwaller, Benjamin (2018) Investigating, Optimizing, and Emulating Candidate Architectures for On-Board Space Processing. Master's Thesis, University of Pittsburgh. (Unpublished)

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Abstract

With increasing computational demands in the defense and commercial industries, future space missions will require new, high-performance architectures. Extensive research, benchmarking, and analysis of candidate architectures is required before performing the expensive, time-consuming process of radiation-hardening on suitable devices. In this work, we first compare two such candidate architectures: the Texas Instruments KeyStone II octa-core DSP and the ARM Cortex-A53 quad-core CPU. We evaluate the performance of a key kernel used in space applications, the Fast Fourier Transform (FFT), and a key space application, the complex ambiguity function (CAF), on each architecture. We also develop and evaluate a direct-memory access scheme to take advantage of the KeyStone II architecture to perform FFTs. The KeyStone II’s batched 1D-FFT performance-per-watt is 4.1 times greater than the ARM Cortex-A53 and the CAF performance-per-watt is 1.8 times greater. Next, we develop and employ an emulator to study the performance of the High-Performance Spaceflight Computing (HPSC) processor. The HPSC processor is a future architecture under development by Boeing and funded by NASA and AFRL for their future space missions. HPSC is comprised of “chiplets” which have two quad-core ARM Cortex-A53 CPUs connected by an AMBA bus. These chiplets can be connected by different serial interfaces depending on mission needs. By employing two ARM platforms, an octa-core ARM architecture and two quad-core ARM architectures connected by Ethernet, we project HPSC performance for FFTs and another key space application: synthetic-aperture radar (SAR). We project that SAR will scale well on a multi-chiplet platform with a performance gain of 2.94 over a single US+ board when using two connected chiplets. Our research provides new insights on the tradeoffs encountered when parallelizing functions on these candidate architectures, including novel optimization techniques for each architectures.


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Details

Item Type: University of Pittsburgh ETD
Status: Unpublished
Creators/Authors:
CreatorsEmailPitt UsernameORCID
Schwaller, Benjaminschwaller@pitt.edubjs1230000-0002-9282-8977
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairGeorge, Alanalan.george@pitt.edu
Committee MemberYang, Junjuy9@pitt.edu
Committee MemberJones, Alexakjones@pitt.edyu
Date: 11 June 2018
Date Type: Publication
Defense Date: 2018
Approval Date: 11 June 2018
Submission Date: 6 April 2018
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 81
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical and Computer Engineering
Degree: MS - Master of Science
Thesis Type: Master's Thesis
Refereed: Yes
Uncontrolled Keywords: Space processing Keystone II ARM HPSC
Date Deposited: 11 Jun 2018 17:54
Last Modified: 11 Jun 2018 17:54
URI: http://d-scholarship.pitt.edu/id/eprint/34136

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