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Architectural Techniques for Disturbance Mitigation in Future Memory Systems

Seyedzadeh Delcheh, Seyed Mohammad (2019) Architectural Techniques for Disturbance Mitigation in Future Memory Systems. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

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With the recent advancements of CMOS technology, scaling down the feature size has improved memory capacity, power, performance and cost. However, such dramatic progress in memory technology has increasingly made the precise control of the manufacturing process below 22nm more difficult. In spite of all these virtues, the technology scaling road map predicts significant process variation from cell-to-cell. It also predicts electromagnetic disturbances among memory cells that easily deviate their circuit characterizations from design goals and pose threats to the reliability, energy efficiency and security.

This dissertation proposes simple, energy-efficient and low-overhead techniques that combat the challenges resulting from technology scaling in future memory systems. Specifically, this dissertation investigates solutions tuned to particular types of disturbance challenges, such as inter-cell or intra-cell disturbance, that are energy efficient while guaranteeing memory reliability.

The contribution of this dissertation will be threefold. First, it uses a deterministic
counter-based approach to target the root of inter-cell disturbances in Dynamic random access memory (DRAM) and provide further benefits to overall energy consumption while deterministically mitigating inter-cell disturbances. Second, it uses Markov chains to reason about the reliability of Spin-Transfer Torque Magnetic Random-Access Memory (STT-RAM) that suffers from intra-cell disturbances and then investigates on-demand refresh policies to recover from the persistent effect of such disturbances. Third, It leverages an encoding technique integrated with a novel word level compression scheme to reduce the vulnerability of cells to inter-cell write disturbances in Phase Change Memory (PCM). However, mitigating inter-cell write disturbances and also minimizing the write energy may increase the number of updated PCM cells and result in degraded endurance. Hence, It uses multi-objective optimization to balance the write energy and endurance in PCM cells while mitigating intercell disturbances.

The work in this dissertation provides important insights into how to tackle the critical reliability challenges that high-density memory systems confront in deep scaled technology nodes. It advocates for various memory technologies to guarantee reliability of future memory systems while incurring nominal costs in terms of energy, area and performance.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Seyedzadeh Delcheh, Seyed
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairMelhem, Ramimelhem@cs.pitt.edumelhem
Committee MemberJones, Alexakjones@pitt.eduakjones
Committee MemberZhang, Youtaozhangyt@cs.pitt.eduzhangyt
Committee MemberYang, Junjuy9@pitt.edujuy9
Committee MemberXiong, Fengf.xiong@pitt.eduf.xiong
Thesis AdvisorMelhem, Ramimelhem@cs.pitt.edumelhem
Date: 8 January 2019
Date Type: Publication
Defense Date: 31 August 2018
Approval Date: 8 January 2019
Submission Date: 18 November 2018
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 146
Institution: University of Pittsburgh
Schools and Programs: School of Computing and Information > Computer Science
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: Technology Scaling, Inter/Intra Cell Disturbance, STT-RAM, DRAM, PCM
Date Deposited: 08 Jan 2019 16:37
Last Modified: 08 Jan 2019 16:37

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