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H-ORAM: A Cacheable ORAM Interface for Efficient I/O Accesses

Liu, Liang and Wang, Rujia and Yang, Jun and Zhang, Youtao (2019) H-ORAM: A Cacheable ORAM Interface for Efficient I/O Accesses. Master's Thesis, University of Pittsburgh. (Unpublished)

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Oblivious RAM (ORAM) is an effective security primitive to prevent access pattern
leakage. By adding redundant memory accesses, ORAM prevents attackers from revealing the
patterns in the access sequences. However, ORAM tends to introduce a huge degradation on the
performance. With growing address space to be protected, ORAM has to store the majority of
data in the lower level storage, which further degrades the system performance.
In this paper, we propose Hybrid ORAM (H-ORAM), a novel ORAM primitive to address
large performance degradation when overflowing the user data to storage. H-ORAM consists of a
batch scheduling scheme for enhancing the memory bandwidth usage, and a novel ORAM
interface that returns data without waiting for the I/O access each time. We evaluate H-ORAM on
a real machine implementation. The experimental results show that that H-ORAM outperforms the
state-of-the-art Path ORAM by 19.8x for a small data set and 22.9x for a large data set.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Liu, Lianglil125@pitt.edulil125
Wang, Rujiarujia.w@pitt.edurujia.w
Yang, Junjuy9@pitt.edujuy9
Zhang, Youtaoyoutao@pitt.eduyoutao
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairYang, Junjuy9@pitt.edujuy9
Committee MemberDickerson, Samueldickerson@pitt.edudickerson
Committee MemberHu, Jingtongjthu@pitt.edujthu
Date: 18 June 2019
Date Type: Publication
Defense Date: 4 March 2019
Approval Date: 18 June 2019
Submission Date: 5 April 2019
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 44
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical and Computer Engineering
Degree: MS - Master of Science
Thesis Type: Master's Thesis
Refereed: Yes
Uncontrolled Keywords: ObliviousRAM,memorysecurity,I/Oaccesses,scheduling,obliviousshuffle
Date Deposited: 18 Jun 2019 17:45
Last Modified: 18 Jun 2019 17:45


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