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Achieving Reliable and Sustainable Next-Generation Memories

Kline Jr, Donald (2019) Achieving Reliable and Sustainable Next-Generation Memories. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

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Conventional memory technology scaling has introduced reliability challenges due to dysfunctional, improperly formed cells and crosstalk from increased cell proximity. Furthermore, as the manufacturing effort becomes increasingly complex due to these deeply scaled technologies, holistic sustainability is negatively impacted. The development of new memory technologies can help overcome the capacitor scaling limitations of DRAM. However, these technologies have their own reliability concerns, such as limited write endurance in the case of Phase Change Memories (PCM). Moreover, emerging system requirements, such as in-memory encryption to protect sensitive or private data and operation in harsh environments create additional challenges that must be addressed in the context of reliability and sustainability. This dissertation provides new multifactor and ultimately unified solutions to address many of these concerns in the same system.

In particular, my contributions toward mitigating these issues are as follows. I present GreenChip and GreenAsic, which together provide the first tools to holistically evaluate new computer architecture, chip, and memory design concepts for sustainability. These tools provide detailed estimates of manufacturing and operational-phase metrics for different computing workloads and deployment scenarios. Using GreenChip, I examined existing DRAM reliability techniques in the context of their holistic sustainability impact, including my own technique to mitigate bitline crosstalk. For PCM, I provided a new reliability technique with no additional storage overhead that substantially increases the lifetime of an encrypted memory system. To provide bit-level error correction, I developed compact linked-list and Bloom-filter-based bit-level fault map structures, that provide unprecedented levels of error tabulation, combined with my own novel error correction and lifetime extension approaches based on these maps for less area than traditional ECC. In particular, FaME, can correct N faults using N bits when utilizing a bit-level fault map. For operation in harsh environments, I created a triple modular redundancy (TMR) pointer-based fault map, HOTH, which specifically protects cells shown to be weak to radiation. Finally, to combine the analyses of holistic sustainability and memory lifetime, I created the LARS technique, which adjusts the GreenChip indifference analysis to account for the additional sustainability benefit provided by increased reliability and lifetime.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Kline Jr, Donalddek61@pittedudek610000-0002-4414-1513
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairJones, Alexakjones@pitt.eduakjones
Committee MemberMelhem, Ramimelhem@cs.pitt.edumelhem
Committee MemberYang, Junjuy9@pitt.edujuy9
Committee MemberHu, Jingtongjthu@pitt.edujthu
Committee MemberXiong, Fengf.xiong@pitt.eduf.xiong
Date: 10 September 2019
Date Type: Publication
Defense Date: 9 July 2019
Approval Date: 10 September 2019
Submission Date: 10 July 2019
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 146
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical and Computer Engineering
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: Memory Reliability Sustainable Computing Emerging Memories Bit-level Faultmaps
Date Deposited: 10 Sep 2019 20:02
Last Modified: 10 Sep 2019 20:02


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