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Improving Performance and Endurance for Crossbar Resistive Memory

Wen, Wen (2020) Improving Performance and Endurance for Crossbar Resistive Memory. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

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Resistive Memory (ReRAM) has emerged as a promising non-volatile memory technology that may replace a significant portion of DRAM in future computer systems. When adopting crossbar architecture, ReRAM cell can achieve the smallest theoretical size in fabrication, ideally for constructing dense memory with large capacity. However, crossbar cell structure suffers from severe performance and endurance degradations, which come from large voltage drops on long wires.

In this dissertation, I first study the correlation between the ReRAM cell switching latency and the number of cells in low resistant state (LRS) along bitlines, and propose to dynamically speed up write operations based on bitline data patterns. By leveraging the intrinsic in-memory processing capability of ReRAM crossbars, a low overhead runtime profiler that effectively tracks the data patterns in different bitlines is proposed. To achieve further write latency reduction, data compression and row address dependent memory data layout are employed to reduce the numbers of LRS cells on bitlines. Moreover, two optimization techniques are presented to mitigate energy overhead brought by bitline data patterns tracking.

Second, I propose XWL, a novel table-based wear leveling scheme for ReRAM crossbars and study the correlation between write endurance and voltage stress in ReRAM crossbars. By estimating and tracking the effective write stress to different rows at runtime, XWL chooses the ones that are stressed the most to mitigate.

Additionally, two extended scenarios are further examined for the performance and endurance issues in neural network accelerators as well as 3D vertical ReRAM (3D-VRAM) arrays. For the ReRAM crossbar-based accelerators, by exploiting the wearing out mechanism of ReRAM cell, a novel comprehensive framework, ReNEW, is proposed to enhance the lifetime of the ReRAM crossbar-based accelerators, particularly for neural network training. To reduce the write latency in 3D-VRAM arrays, a collection of techniques, including an in-memory data encoding scheme, a data pattern estimator for assessing cell resistance distributions, and a write time reduction scheme that opportunistically reduces RESET latency with runtime data patterns, are devised.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Wen, Wenwew55@pitt.eduwew55
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairYang, Junjuy9@pitt.edujuy9
Committee CoChairZhang, Youtaozhangyt@cs.pitt.eduyoutao
Committee MemberMiskov-Zivanov, Natasanmzivanov@pitt.edunmzivanov
Committee MemberHu, Jingtongjthu@pitt.edujthu
Committee MemberXiong, Fengf.xiong@pitt.eduf.xiong
Committee MemberHe, Daqingdah44@pitt.edudah44
Date: 28 September 2020
Date Type: Publication
Defense Date: 19 June 2020
Approval Date: 28 September 2020
Submission Date: 1 July 2020
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 140
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical and Computer Engineering
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: Resistive Memory, Data Pattern, Crossbar Array, Write Performance, Endurance
Date Deposited: 28 Sep 2020 20:06
Last Modified: 28 Sep 2020 20:06


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