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RISC-V Benchmarking for Onboard Sensor Processing

Cannizzaro, Michael James (2021) RISC-V Benchmarking for Onboard Sensor Processing. Master's Thesis, University of Pittsburgh. (Unpublished)

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When designing embedded systems, especially for space-computing needs, finding the ideal balance between size, weight, power, and cost (SWaP-C) is the primary goal in the processor selection process. One variable that can have a significant impact on the tradeoffs between performance and power consumption is the processor architecture. Widely adopted architectures such as the ARM Cortex-A series have gained popularity due to their favorable combination of high performance and low power consumption. The RISC-V architecture presents a compelling alternative in part due to its modular instruction set, collaborative development approach, and open-source nature. The recent introduction of a RISC-V processor in the Microchip PolarFire SoC enables performance and power consumption comparisons to be made with competing architectures using application and kernel benchmarks. For application benchmarking, this research employs image-processing apps including a histogram equalizer, Sobel filter, and image tiler to describe real-world performance. To gain additional insight into architectural characteristics, kernel benchmarks that perform common sensor processing operations such as matrix multiplication and convolution can be used. Additionally, the CoreMark synthetic benchmark suite is used to quantify overall performance. This study considers several architectures and space-grade computer systems, including the ARM Cortex-A9 SHREC Space Processor, the ARM Cortex-A53 Boeing High Performance Space Computing (HPSC) platform, and the Power e5500 BAE Systems RAD5545 processor. Facsimiles are leveraged for the HPSC and the RAD5545 platforms. Both single- and multi-core performance are considered in this study. The PolarFire SoC achieves approximately 3.13 CoreMarks per MHz and 15.63 CoreMarks per milliwatt, demonstrating competitive performance and power consumption characteristics under single-threaded workloads. However, RISC-V presents mixed results during multiprocessing, with execution times that are average at best. Additionally, while matrix multiplication and addition yield high parallel efficiencies, convolution and transpose are less efficient. Dynamic energy consumption results for the PolarFire SoC are also generally average, but the platform does achieve significant reductions in dynamic energy consumption during increased parallel workloads. While the RISC-V architecture does not present ideal benchmark results, it remains competitive in terms of performance and power consumption, with future extensions to the instruction set only further enabling its potential for space applications.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Cannizzaro, Michael Jamesmjc153@pitt.edumjc1530000-0002-0883-8153
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Thesis AdvisorGeorge, Alan
Committee MemberDickerson,
Committee MemberYang,
Date: 13 June 2021
Date Type: Publication
Defense Date: 30 March 2021
Approval Date: 13 June 2021
Submission Date: 19 March 2021
Access Restriction: 1 year -- Restrict access to University of Pittsburgh for a period of 1 year.
Number of Pages: 59
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical and Computer Engineering
Degree: MSEE - Master of Science in Electrical Engineering
Thesis Type: Master's Thesis
Refereed: Yes
Uncontrolled Keywords: Benchmark, Processor Architecture, RISC-V, Sensor Processing, SoC, Space Computing
Date Deposited: 13 Jun 2021 18:33
Last Modified: 13 Jun 2022 05:15


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