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A Fully-Integrated Shift-Register DLDO Using Pull-Up and Pull-Down Devices

Shen, Junyi (2021) A Fully-Integrated Shift-Register DLDO Using Pull-Up and Pull-Down Devices. Master's Thesis, University of Pittsburgh. (Unpublished)

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The digital low-drop-out regulator (DLDO) regulates its output voltage and provides a fast transient response during a load change. DLDO is an essential part for managing power consumption of multiple supply voltage domains in modern system-on-chip (SOC) designs. One of the conventional DLDO designs uses a shift register (SR) to regulate the output voltage by controlling shift directions of the output bits. The shift register changes the output bits sequentially, hence providing high accuracy in steady state. However, due to this characteristic, the SR-based DLDO cannot provide a fast transient response during a load change. Higher clock frequency during the load transient can solve the problem, but it results in higher power consumption. To overcome this disadvantage, this paper offers a fully-integrated SR-based DLDO with pull-up and pull-down switches. It discusses optimization of the pull-up and pull-down switch size in detail.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Shen, Junyijus108@pitt.edujus108
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Thesis AdvisorLee,
Committee MemberDickerson,
Committee MemberKubendran,
Date: 13 June 2021
Date Type: Publication
Defense Date: 5 March 2021
Approval Date: 13 June 2021
Submission Date: 20 March 2021
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 40
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical and Computer Engineering
Degree: MS - Master of Science
Thesis Type: Master's Thesis
Refereed: Yes
Uncontrolled Keywords: Digital LDO, Shift Register, pull-up and pull-down devices
Date Deposited: 13 Jun 2021 18:40
Last Modified: 13 Jun 2021 18:40


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