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Dynamic Binary Translation for Embedded Systems with Scratchpad Memory

Baiocchi Paredes, Jose Americo (2012) Dynamic Binary Translation for Embedded Systems with Scratchpad Memory. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

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Embedded software development has recently changed with advances in computing. Rather than fully co-designing software and hardware to perform a relatively simple task, nowadays embedded and mobile devices are designed as a platform where multiple applications can be run, new applications can be added, and existing applications can be updated. In this scenario, traditional constraints in embedded systems design (i.e., performance, memory and energy consumption and real-time guarantees) are more difficult to address. New concerns (e.g., security) have become important and increase software complexity as well.

In general-purpose systems, Dynamic Binary Translation (DBT) has been used to address these issues with services such as Just-In-Time (JIT) compilation, dynamic optimization, virtualization, power management and code security. In embedded systems, however, DBT is not usually employed due to performance, memory and power overhead.

This dissertation presents StrataX, a low-overhead DBT framework for embedded systems. StrataX addresses the challenges faced by DBT in embedded systems using novel techniques. To reduce DBT overhead, StrataX loads code from NAND-Flash storage and translates it into a Scratchpad Memory (SPM), a software-managed on-chip SRAM with limited capacity. SPM has similar access latency as a hardware cache, but consumes less power and chip area.

StrataX manages SPM as a software instruction cache, and employs victim compression and pinning to reduce retranslation cost and capture frequently executed code in the SPM. To prevent performance loss due to excessive code expansion, StrataX minimizes the amount of code inserted by DBT to maintain control of program execution. When a hardware instruction cache is available, StrataX dynamically partitions translated code among the SPM and main memory. With these techniques, StrataX has low performance overhead relative to native execution for MiBench programs. Further, it simplifies embedded software and hardware design by operating transparently to applications without any special hardware support. StrataX achieves sufficiently low overhead to make it feasible to use DBT in embedded systems to address important design goals and requirements.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Baiocchi Paredes, Jose
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairChilders, Bruce R.childers@cs.pitt.eduCHILDERS
Committee MemberCho, Sangyeuncho@cs.pitt.eduSANGYEUN
Committee MemberZhang, Youtaozhangyt@cs.pitt.eduYOUTAO
Committee MemberDavidson, Jack
Date: 31 January 2012
Date Type: Publication
Defense Date: 11 November 2011
Approval Date: 31 January 2012
Submission Date: 10 November 2011
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 155
Institution: University of Pittsburgh
Schools and Programs: Dietrich School of Arts and Sciences > Computer Science
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: Dynamic Binary Translation, Code Cache Management, Embedded Systems, System-on-Chip, Scratchpad Memory, NAND Flash, Demand Paging, Code Compression, Footprint Reduction, Software Caching
Related URLs:
Date Deposited: 31 Jan 2012 15:36
Last Modified: 15 Nov 2016 13:35


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