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Ahn, Jiyong (2002) A CUSTOM ARCHITECTURE FOR DIGITAL LOGIC SIMULATION. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

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As VLSI technology advances, designers can pack larger circuits into a single chip. According to the International Technology Roadmap for Semiconductors, in the year 2005, VLSI circuit technology will produce chips with 200 million transistors in total, 40 million logic gates, 2 to 3.5 GHz clock rates, and 160 watts of power-consumption. Recently, Intel announced that they will produce a billion-transistor processor before 2010. However, current design methodologies can only handle tens of millions of transistors in a single design. In this thesis, we focus on the problem of simulating large digital devices at the gate level. While many software solutions to gate-level simulation exist, their performance is limited by the underlying general-purpose workstation architecture. This research defines an architecture that is specifically designed for gate-level logic simulation that is at least an order of magnitude faster than software running on a workstation. We present a custom processor and memory architecture design that can simulate a gate level design orders of magnitude faster than the software simulation, while maintaining 4-levels of signal strength. New primitives are presented and shown to significantly reduce the complexity of simulation. Unlike most simulators, which only use zero or unit time delay models, this research provides a mechanism to handle more complex full-timing delay model at pico-second accuracy. Experimental results and a working prototype will also be presented.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Ahn, Jiyongahn@pitt.eduAHN
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairHoare, Raymond R.hoare@pitt.eduHOARE
Committee MemberCain, James T.
Committee MemberMickle, Marlin H.
Committee MemberBesterfield-Sacre, Mary E.
Committee MemberHoelzeman, Ronald G.
Date: 22 March 2002
Date Type: Completion
Defense Date: 30 January 2002
Approval Date: 22 March 2002
Submission Date: 6 March 2002
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical Engineering
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: Behavioral Modeling; Discrete Event Simulation; Hardware Logic Simulator
Other ID:, etd-03062002-100652
Date Deposited: 10 Nov 2011 19:32
Last Modified: 15 Nov 2016 13:36


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