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Static Timing Analysis Based Transformations of Super-Complex Instruction Set Hardware Functions

Ihrig, Colin James (2008) Static Timing Analysis Based Transformations of Super-Complex Instruction Set Hardware Functions. Master's Thesis, University of Pittsburgh. (Unpublished)

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Application specific hardware implementations are an increasingly popular way of reducing execution time and power consumption in embedded systems. This application specific hardware typically consumes a small fraction of the execution time and power consumption that the equivalent software code would require. Modern electronic design automation (EDA) tools can be used to apply a variety of transformations to hardware blocks in an effort to achieve additional performance and power savings. A number of such transformations require a tool with knowledge of the designs' timing characteristics. This thesis describes a static timing analyzer and two timing analysis based design automation tools. The static timing analyzer estimates the worst-case timing characteristics of a hardware data flow graph. These hardware data flow graphs are intermediate representations generated within a C to VHDL hardware acceleration compiler. Two EDA tools were then developed which utilize static timing analysis. An automated pipelining tool was developed to increase the throughput of large blocks of combinational logic generated by the hardware acceleration compiler. Another tool was designed in an attempt to mitigate power consumption resulting from extraneous combinational switching. By inserting special signal buffers, known as delay elements, with preselected propagation delays, combinational functional units can be kept inactive until their inputs have stabilized. The hardware descriptions generated by both tools were synthesized, simulated, and power profiled using existing commercial EDA tools. The results show that pipelining leads to an average performance increase of 3.3x, while delay elements saved between 25% and 33% of the power consumption when tested on a set of signal and image processing benchmarks.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Ihrig, Colin Jamescji3@pitt.eduCJI3
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairJones, Alex K.
Committee MemberYang, Jun
Committee MemberLevitan, Steven
Date: 9 June 2008
Date Type: Completion
Defense Date: 6 March 2008
Approval Date: 9 June 2008
Submission Date: 10 March 2008
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Computer Engineering
Degree: MS - Master of Science
Thesis Type: Master's Thesis
Refereed: Yes
Uncontrolled Keywords: delay elements; low power; pipelining; reduced glitching; reduced switching; static timing analysis; SuperCISC
Other ID:, etd-03102008-120235
Date Deposited: 10 Nov 2011 19:32
Last Modified: 15 Nov 2016 13:37


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