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An Implementation of a Three Dimensional Computational Pipeline with Minimal Latency and Maximum Throughput for LU Factorization Using Field Programmable Gate Arrays

Henciak, Edward Thomas (2008) An Implementation of a Three Dimensional Computational Pipeline with Minimal Latency and Maximum Throughput for LU Factorization Using Field Programmable Gate Arrays. Master's Thesis, University of Pittsburgh. (Unpublished)

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Traditionally, computationally intense algebraic functions such as LU factorization are solved using complex systems such as supercomputers, parallel processing systems, and non-dedicated computing clusters. While these solutions are adequate for some problems, they typically suffer from classic parallel processing issues such as communication overhead, complex scheduling algorithms, and cost. Moreover, they are not feasible for embedded applications. Extremely high performance solutions are sometimes implemented using costly, custom hardware such as Application Specific Integrated Circuits (ASICs). Unfortunately, the design, implementation, and verification of ASICs has become cost prohibitive and such solutions are only feasible if the end design is to be manufactured in very high volumes. As a result, many proposed architectures to solve specific problems lie dormant because they are simply too expensive to realize.In recent years, advancements in Field Programmable Gate Array (FPGA) technology allow engineers to map complex algorithms to logic gates while achieving performance similar to ASIC technology. This thesis demonstrates the feasibility of the implementation of a three dimensional pipeline designed to solve LU factorization using FPGAs based on an architecture proposed nearly 10 years ago when a technology to implement such an architecture either did not exist or was too costly to implement.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Henciak, Edward
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee CoChairCain, James T.jtc@pitt.eduJTC
Committee CoChairMickle, Marlinmickle@pitt.eduMICKLE
Committee MemberBoston, John R.bbn@pitt.eduBBN
Committee MemberHoelzeman, Ronald G.hoelzema@pitt.eduHOELZEMA
Date: 8 September 2008
Date Type: Completion
Defense Date: 4 April 2008
Approval Date: 8 September 2008
Submission Date: 23 March 2008
Access Restriction: 5 year -- Restrict access to University of Pittsburgh for a period of 5 years.
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical Engineering
Degree: MSEE - Master of Science in Electrical Engineering
Thesis Type: Master's Thesis
Refereed: Yes
Uncontrolled Keywords: Altera; ASIC; computer architecture; Crout Elimination; FPGA; Linear Simultaneous Equations; LSE; LU Factorization; Xilinx
Other ID:, etd-03232008-175844
Date Deposited: 10 Nov 2011 19:32
Last Modified: 15 Nov 2016 13:37


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