Lee, Hyunjin A.
(2011)
Fault- and Yield-Aware On-Chip Memory Design and Management.
Doctoral Dissertation, University of Pittsburgh.
(Unpublished)
Abstract
Ever decreasing device size causes more frequent hard faults, which becomes a serious burden to processor design and yield management. This problem is particularly pronounced in the on-chip memory which consumes up to 70% of a processor' s total chip area. Traditional circuit-level techniques, such as redundancy and error correction code, become less effective in error-prevalent environments because of their large area overhead. In this work, we suggest an architectural solution to building reliable on-chip memory in the future processor environment. Our approaches have two parts, a design framework and architectural techniques for on-chip memory structures. Our design framework provides important architectural evaluation metrics such as yield, area, and performance based on low level defects and process variations parameters. Processor architects can quickly evaluate their designs' characteristics in terms of yield, area, and performance. With the framework, we develop architectural yield enhancement solutions for on-chip memory structures including L1 cache, L2 cache and directory memory. Our proposed solutions greatly improve yield with negligible area and performance overhead. Furthermore, we develop a decoupled yield model of compute cores and L2 caches in CMPs, which show that there will be many more L2 caches than compute cores in a chip. We propose efficient utilization techniques for excess caches. Evaluation results show that excess caches significantly improve overall performance of CMPs.
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Details
| Item Type: |
University of Pittsburgh ETD
|
| Status: |
Unpublished |
| Creators/Authors: |
|
| ETD Committee: |
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| Date: |
28 September 2011 |
| Date Type: |
Completion |
| Defense Date: |
13 April 2011 |
| Approval Date: |
28 September 2011 |
| Submission Date: |
17 June 2011 |
| Access Restriction: |
No restriction; Release the ETD for access worldwide immediately. |
| Institution: |
University of Pittsburgh |
| Schools and Programs: |
Dietrich School of Arts and Sciences > Computer Science |
| Degree: |
PhD - Doctor of Philosophy |
| Thesis Type: |
Doctoral Dissertation |
| Refereed: |
Yes |
| Uncontrolled Keywords: |
Computer Architecture; fault tolerance; on-chip memory; yield |
| Other ID: |
http://etd.library.pitt.edu/ETD/available/etd-06172011-094532/, etd-06172011-094532 |
| Date Deposited: |
10 Nov 2011 19:47 |
| Last Modified: |
15 Nov 2016 13:44 |
| URI: |
http://d-scholarship.pitt.edu/id/eprint/8137 |
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