Bakos, Jason Daniel
(2005)
Lightweight Hierarchical Error Control Codes for Multi-Bit Differential Channels.
Doctoral Dissertation, University of Pittsburgh.
(Unpublished)
Abstract
This dissertation describes a new class of non-linear block codes called "Lightweight Hierarchical Error Control Codes (LHECC)." LHECC is designed to operate over system-level interconnects such as network-on-chip, inter-chip, and backplane interconnects. LHECC provides these interconnects with powerful error correction capability and thus effectively increases signal integrity and noise immunity. As a result, these interconnects may carry data with lower signal power and/or higher transmission rates. LHECC is designed such that support for it may be tightly integrated into high-speed, low-latency system-level I/O interfaces. Encoding and decoding may be performed at system core speeds with low chip area requirements.LHECC is optimized for a new type of high-performance system-level interconnect technology called Multi-Bit Differential Signaling (MBDS). MBDS channels require the use of a physical-layer channel code called "N choose M (nCm)" encoding, where each channel is restricted to a symbol set such that half of the bits in each symbol are 1-bits. These symbol sets have properties such as inherent error detection capability and unused symbol space. These properties are used to give MBDS-based system-level interconnects an arbitrary error correction capability with low or zero information overhead. This is achieved by hierarchical encoding, where a portion of source data is encoded into a "high-level" block code while the remainder of the data is encoded into a "low-level" code by choosing particular nCm symbols from symbol subsets specified by the high-level encoding.This dissertation presents the following. First, it provides a theoretical study of LHECC and illustrates its effectiveness at achieving low-overhead error control for system-level interconnects. Second, it provides example implementations of efficient LHECC encoder and decoder architectures that are capable of operating at speeds necessary for high-performance system-level channels. Third, it describes an experimental technique to verify the effectiveness of these codes, where interconnect error behavior is captured using channel and noise models over a range of transmission rates and noise characteristics. Results obtained through simulation of these models characterize the effectiveness of LHECC. Using this method, system-level interconnects that utilize this new encoding technique are shown to have significantly higher noise immunity than those without.
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Details
| Item Type: |
University of Pittsburgh ETD
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| Status: |
Unpublished |
| Creators/Authors: |
|
| ETD Committee: |
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| Date: |
3 October 2005 |
| Date Type: |
Completion |
| Defense Date: |
28 June 2005 |
| Approval Date: |
3 October 2005 |
| Submission Date: |
19 July 2005 |
| Access Restriction: |
No restriction; Release the ETD for access worldwide immediately. |
| Institution: |
University of Pittsburgh |
| Schools and Programs: |
Dietrich School of Arts and Sciences > Computer Science |
| Degree: |
PhD - Doctor of Philosophy |
| Thesis Type: |
Doctoral Dissertation |
| Refereed: |
Yes |
| Uncontrolled Keywords: |
computer engineering; data encoding; interconnect; low-power; communications; signaling; error correction codes |
| Other ID: |
http://etd.library.pitt.edu/ETD/available/etd-07192005-114823/, etd-07192005-114823 |
| Date Deposited: |
10 Nov 2011 19:52 |
| Last Modified: |
15 Nov 2016 13:46 |
| URI: |
http://d-scholarship.pitt.edu/id/eprint/8443 |
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