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Simulation Of Multi-core Systems And Interconnections And Evaluation Of Fat-Mesh Networks

Zhang, Yu (2009) Simulation Of Multi-core Systems And Interconnections And Evaluation Of Fat-Mesh Networks. Master's Thesis, University of Pittsburgh. (Unpublished)

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Simulators are very important in computer architecture research as they enable the exploration of new architectures to obtain detailed performance evaluation without building costly physical hardware. Simulation is even more critical to study future many-core architectures as it provides the opportunity to assess currently non-existing computer systems. In this thesis, a multiprocessor simulator is presented based on a cycle accurate architecture simulator called SESC. The shared L2 cache system is extended into a distributed shared cache (DSC) with a directory-based cache coherency protocol. A mesh network module is extended and integrated into SESC to replace the bus for scalable inter-processor communication. While these efforts complete an extended multiprocessor simulation infrastructure, two interconnection enhancements are proposed and evaluated. A novel non-uniform fat-mesh network structure similar to the idea of fat-tree is proposed. This non-uniform mesh network takes advantage of the average traffic pattern, typically all-to-all in DSC, to dedicate additional links for connections with heavy traffic (e.g., near the center) and fewer links for lighter traffic (e.g., near the periphery). Two fat-mesh schemes are implemented based on different routing algorithms. Analytical fat-mesh models are constructed by presenting the expressions for the traffic requirements of personalized all-to-all traffic. Performance improvements over the uniform mesh are demonstrated in the results from the simulator. A hybrid network consisting of one packet switching plane and multiple circuit switching planes is constructed as the second enhancement. The circuit switching planes provide fast paths between neighbors with heavy communication traffic. A compiler technique that abstracts the symbolic expressions of benchmarks' communication patterns can be used to help facilitate the circuit establishment.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Zhang, Yuyuz28@pitt.eduYUZ28
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairJones, Alex Kakjones@ece.pitt.eduAKJONES
Committee MemberYang, Junjunyang@engr.pitt.eduJUY9
Committee MemberLevitan, Stevenlevitan@pitt.eduLEVITAN
Date: 28 January 2009
Date Type: Completion
Defense Date: 10 November 2008
Approval Date: 28 January 2009
Submission Date: 13 November 2008
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical Engineering
Degree: MSEE - Master of Science in Electrical Engineering
Thesis Type: Master's Thesis
Refereed: Yes
Uncontrolled Keywords: Circuit Switching; Network on Chip; Symbolic Analysis; Architecture Simulator; Chip Multiprocessor; Fat Mesh
Other ID:, etd-11132008-165506
Date Deposited: 10 Nov 2011 20:04
Last Modified: 15 Nov 2016 13:51


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