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Hybrid Caching for Chip Multiprocessors Using Compiler-Based Data Classification

Li, Yong (2011) Hybrid Caching for Chip Multiprocessors Using Compiler-Based Data Classification. Master's Thesis, University of Pittsburgh.

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    Abstract

    The high performance delivered by modern computer system keeps scaling with an increasingnumber of processors connected using distributed network on-chip. As a result, memory accesslatency, largely dominated by remote data cache access and inter-processor communication, is becoming a critical performance bottleneck. To release this problem, it is necessary to localize data access as much as possible while keep efficient on-chip cache memory utilization. Achieving this however, is application dependent and needs a keen insight into the memory access characteristics of the applications. This thesis demonstrates how using fairly simple thus inexpensive compiler analysis memory accesses can be classified into private data access and shared data access. In addition, we introduce a third classification named probably private access and demonstrate the impact of this category compared to traditional private and shared memory classification. The memory access classification information from the compiler analysis is then provided to the runtime system through a modified memory allocator and page table to facilitate a hybrid private-shared caching technique. The hybrid cache mechanism is aware of different data access classification and adopts appropriate placement and search policies accordingly to improve performance. Our analysis demonstrates that many applications have a significant amount of both private and shared data and that compiler analysis can identify the private data effectively for many applications. Experimentsresults show that the implemented hybrid caching scheme achieves 4.03% performance improvement over state of the art NUCA-base caching.


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    Item Type: University of Pittsburgh ETD
    Creators/Authors:
    CreatorsEmailORCID
    Li, Yongyol26@pitt.edu
    ETD Committee:
    ETD Committee TypeCommittee MemberEmailORCID
    Committee ChairJones, Alex Kakjones@ece.pitt.edu
    Committee MemberMelhem, Ramimelhem@cs.pitt.edu
    Committee MemberCho, Sangyeun Paulcho@cs.pitt.edu
    Committee MemberZhang, Youtaozhangyt@cs.pitt.edu
    Title: Hybrid Caching for Chip Multiprocessors Using Compiler-Based Data Classification
    Status: Unpublished
    Abstract: The high performance delivered by modern computer system keeps scaling with an increasingnumber of processors connected using distributed network on-chip. As a result, memory accesslatency, largely dominated by remote data cache access and inter-processor communication, is becoming a critical performance bottleneck. To release this problem, it is necessary to localize data access as much as possible while keep efficient on-chip cache memory utilization. Achieving this however, is application dependent and needs a keen insight into the memory access characteristics of the applications. This thesis demonstrates how using fairly simple thus inexpensive compiler analysis memory accesses can be classified into private data access and shared data access. In addition, we introduce a third classification named probably private access and demonstrate the impact of this category compared to traditional private and shared memory classification. The memory access classification information from the compiler analysis is then provided to the runtime system through a modified memory allocator and page table to facilitate a hybrid private-shared caching technique. The hybrid cache mechanism is aware of different data access classification and adopts appropriate placement and search policies accordingly to improve performance. Our analysis demonstrates that many applications have a significant amount of both private and shared data and that compiler analysis can identify the private data effectively for many applications. Experimentsresults show that the implemented hybrid caching scheme achieves 4.03% performance improvement over state of the art NUCA-base caching.
    Date: 26 January 2011
    Date Type: Completion
    Defense Date: 08 November 2010
    Approval Date: 26 January 2011
    Submission Date: 16 November 2010
    Access Restriction: No restriction; The work is available for access worldwide immediately.
    Patent pending: No
    Institution: University of Pittsburgh
    Thesis Type: Master's Thesis
    Refereed: Yes
    Degree: MS - Master of Science
    URN: etd-11162010-142107
    Uncontrolled Keywords: Hybrid Caching Compiler-assisted CMPs
    Schools and Programs: Swanson School of Engineering > Computer Engineering
    Date Deposited: 10 Nov 2011 15:05
    Last Modified: 14 May 2012 09:11
    Other ID: http://etd.library.pitt.edu/ETD/available/etd-11162010-142107/, etd-11162010-142107

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