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Real Time 3-D Graphics Processing Hardware Design using Field-Programmable Gate Arrays.

Warner, James Ryan (2009) Real Time 3-D Graphics Processing Hardware Design using Field-Programmable Gate Arrays. Master's Thesis, University of Pittsburgh. (Unpublished)

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Three dimensional graphics processing requires many complex algebraic and matrix based operations to be performed in real-time. In early stages of graphics processing, such tasks were delegated to a Central Processing Unit (CPU). Over time as more complex graphics rendering was demanded, CPU solutions became inadequate. To meet this demand, custom hardware solutions that take advantage of pipelining and massive parallelism become more preferable to CPU software based solutions. This fact has lead to the many custom hardware solutions that are available today. Since real time graphics processing requires extreme high performance, hardware solutions using Application Specific Integrated Circuits (ASICs) are the standard within the industry. While ASICs are a more than adequate solution for implementing high performance custom hardware, the design, implementation and testing of ASIC based designs are becoming cost prohibitive due to the massive up front verification effort needed as well as the cost of fixing design defects.Field Programmable Gate Arrays (FPGAs) provide an alternative to the ASIC design flow. More importantly, in recent years FPGA technology have begun to improve in performance to the point where ASIC and FPGA performance has become comparable. In addition, FPGAs address many of the issues of the ASIC design flow. The ability to reconfigure FPGAs reduces the upfront verification effort and allows design defects to be fixed easily. This thesis demonstrates that a 3-D graphics processor implementation on and FPGA is feasible by implementing both a two dimensional and three dimensional graphics processor prototype. By using a Xilinx Virtex 5 ML506 FPGA development kit a fully functional wireframe graphics rendering engine is implemented using VHDL and Xilinx's development tools. A VHDL testbench was designed to verify that the graphics engine works functionally. This is followed by synthesizing the design and real hardware and developing test applications to verify functionality and performance of the design. This thesis provides the ground work for push forward the use of FPGA technology in graphics processing applications.


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Item Type: University of Pittsburgh ETD
Status: Unpublished
CreatorsEmailPitt UsernameORCID
Warner, James, jrw26@pitt.eduJRW26
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairCain, James Tcain@engr.pitt.eduJTC
Committee MemberJones, Alexander Keithakjones@ece.pitt.eduAKJONES
Committee MemberCheng,
Date: 28 January 2009
Date Type: Completion
Defense Date: 18 September 2008
Approval Date: 28 January 2009
Submission Date: 19 November 2008
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical Engineering
Degree: MSEE - Master of Science in Electrical Engineering
Thesis Type: Master's Thesis
Refereed: Yes
Uncontrolled Keywords: 3D Graphics Processing; FPGA; Hardware Design
Other ID:, etd-11192008-182956
Date Deposited: 10 Nov 2011 20:05
Last Modified: 15 Nov 2016 13:51


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