Architectures for Low Energy, Low Latency, High Performance, Durable Multi-/Triple-Level Cell Non-Volatile MemoriesPalangappa, Poovaiah Manavattira (2017) Architectures for Low Energy, Low Latency, High Performance, Durable Multi-/Triple-Level Cell Non-Volatile Memories. Doctoral Dissertation, University of Pittsburgh. (Unpublished)
AbstractMulti-level/triple-level cell non-volatile memories (MLC/TLC NVMs) such as phase-change memory and resistive RAM are the potential replacement candidates for DRAM, which is limited by its high refresh power and poor scaling potential. Besides the benefits of non-volatility (low refresh power) and improved scalability, MLC/TLC NVMs offer high data density and memory capacity over DRAM. However, the viability of MLC/TLC NVMs is limited due to (i) high programming energy/latency and low endurance, (ii) security vulnerability due to non-volatility, and (iii) high read latency. This dissertation presents three architectures for low energy, low latency, high performance, durable MLC/TLC NVMs. First, it presents CompEx/CompEx++ coding, a low overhead scheme that synergistically integrates pattern-based compression with linear block expansion coding to realize simultaneous energy, latency, and lifetime improvements in MLC/TLC NVMs. Second, it presents CASTLE, a Compression-based read-decrypt-free Architecture that provides a read-decrypt-free block-level Secure solution for low laTency, Low Energy durable NVMs. At its core, CASTLE adopts a block-level write-only sequence to eliminate the latency of the read-decrypt steps in state-of-the-art NVM security solutions. Whereas a write-only approach increases cell updates, and thereby energy and latency, CASTLE in- tegrates pattern-based compression and expansion coding to realize energy reductions and lifetime improvements over state-of-the-art. Third, it presents RAPID, a no-overhead critical-word-first read acceleration architecture for improved performance and durability in MLC/TLC NVMs. At its core, RAPID encodes the critical words in a cache line using only the most significant bits (MSbs) of the MLC/TLCs. Since the MSbs of an NVM cell can be decoded using a single read strobe, the data (i.e., critical words) encoded using the MSbs can be decoded with low latency. This dissertation thus addresses the core challenges of write/read energy and latency, endurance, and security of MLC/TLC NVMs and proposes multiple solutions to these challenges. Share
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