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A Hybrid Hardware/Software Architecture That Combines a 4-wide Very Long Instruction Word Software Processor (VLIW) with Application-specific Super-complex Instruction Set Hardware Functions

Kusic, Dara Marie (2005) A Hybrid Hardware/Software Architecture That Combines a 4-wide Very Long Instruction Word Software Processor (VLIW) with Application-specific Super-complex Instruction Set Hardware Functions. Master's Thesis, University of Pittsburgh. (Unpublished)

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Abstract

Application-driven processor designs are becoming increasingly feasible. Today, advances in field-programmable gate array (FPGA) technology are opening the doors to fast and highly-feasible hardware/software co-designed architectures. Over 100,000 FPGA logic array blocks and nearly 100 ASIC multiply-accumulate cores combine with extensible CPU cores to foster the design of configurable, application-driven hybrid processors.This thesis proposes a hardware/software co-designed architecture targeted to an FPGA. The architecture is a very-long instruction-word (VLIW) processor coupled with super-complex instruction set (SuperCISC) hardware co-processors. Results of the VLIW/SuperCISC show performance speedups over a single-issue processor of 9x to 332x, and entire application speedups from 4x to 127x. Contributions of this research include a 4-way VLIW designed from the ground up, a zero-overhead implementation of a hardware/software interface, evaluation of the scalability of shared data stores, examples of application-specific hardware accelerants, a SystemC simulator, and an evaluation of shared memory configurations.


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Details

Item Type: University of Pittsburgh ETD
Status: Unpublished
Creators/Authors:
CreatorsEmailPitt UsernameORCID
Kusic, Dara Mariedmk8607@pitt.eduDMK8607
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairHoare, Raymond Rhoare@engr.pitt.edu
Committee MemberJones, Alex Kakjones@ece.pitt.eduAKJONES
Committee MemberLevitan, Steven Psteve@engr.pitt.eduLEVITAN
Date: 13 October 2005
Date Type: Completion
Defense Date: 6 July 2005
Approval Date: 13 October 2005
Submission Date: 17 July 2005
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical Engineering
Degree: MSEE - Master of Science in Electrical Engineering
Thesis Type: Master's Thesis
Refereed: Yes
Uncontrolled Keywords: application speedup; co-processor; computer architecture; hardware/software interface; hybrid processor; parallel architecture; scaling effects; VLIW
Other ID: http://etd.library.pitt.edu/ETD/available/etd-07172005-165922/, etd-07172005-165922
Date Deposited: 10 Nov 2011 19:51
Last Modified: 15 Nov 2016 13:46
URI: http://d-scholarship.pitt.edu/id/eprint/8412

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