Garrett, Tyler
(2019)
Enabling Intra-Plane Parallel Block Erase to Alleviate the Impact of Garbage Collection.
Master's Thesis, University of Pittsburgh.
(Unpublished)
Abstract
Garbage collection (GC) in NAND flash can significantly decrease I/O performance in SSDs by
copying valid data to other locations, thus blocking incoming I/O requests. To help improve
performance, NAND flash utilizes various advanced commands to increase internal parallelism.
Currently, these commands only parallelize operations across channels, chips, dies, and planes,
neglecting the block-level and below due structural bottlenecks along the data path and risk of
disturbances that can compromise valid data by inducing errors. However, due to the triple-well
structure of the NAND flash plane architecture and erasing procedure, it is possible to erase
multiple blocks within a plane, in parallel, without being restricted by structural limitations or
diminishing the integrity of the valid data. The number of page movements due to multiple block
erases can be restrained so as to bound the overhead per GC. Moreover, more capacity can be
reclaimed per GC which delays future GCs and effectively reduces their frequency. Such an
Intra-Plane Parallel Block Erase (IPPBE) in turn diminishes the impact of GC on incoming
requests, improving their response times. Experimental results show that IPPBE can reduce the
time spent performing GC by up to 50.7% and 33.6% on average, read/write response time by up
to 47.0%/45.4% and 16.5%/14.8% on average respectively, page movements by up to 52.2% and
26.6% on average, and blocks erased by up to 14.2% and 3.6% on average. An energy analysis
conducted indicates that by reducing the number of page copies and the number of block erases,
the energy cost of garbage collection can be reduced up to 44.1% and 19.3% on average.
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Details
| Item Type: |
University of Pittsburgh ETD
|
| Status: |
Unpublished |
| Creators/Authors: |
| Creators | Email | Pitt Username | ORCID  |
|---|
| Garrett, Tyler | tmg61@pitt.edu | tmg61@pitt.edu | |
|
| ETD Committee: |
|
| Date: |
23 January 2019 |
| Date Type: |
Publication |
| Defense Date: |
12 November 2018 |
| Approval Date: |
23 January 2019 |
| Submission Date: |
13 November 2018 |
| Access Restriction: |
No restriction; Release the ETD for access worldwide immediately. |
| Number of Pages: |
54 |
| Institution: |
University of Pittsburgh |
| Schools and Programs: |
Swanson School of Engineering > Electrical and Computer Engineering |
| Degree: |
MS - Master of Science |
| Thesis Type: |
Master's Thesis |
| Refereed: |
Yes |
| Uncontrolled Keywords: |
NAND Flash Memory, Storage, Computer Architecture |
| Date Deposited: |
23 Jan 2019 15:54 |
| Last Modified: |
23 Jan 2019 15:54 |
| URI: |
http://d-scholarship.pitt.edu/id/eprint/35490 |
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