Lucas, Owen
(2024)
FPGA Acceleration of k-mer Counting using On-Chip HBM2 and oneAPI.
Master's Thesis, University of Pittsburgh.
(Unpublished)
Abstract
Counting substrings of an arbitrary length k (k -mers) is the single most time-consuming step of de novo genome sequencing. Sequencing machines generate large quantities of data (>100s of GBs per genome). Processing this genetic information requires frequent memory accesses into data structures considerably larger than available cache, leading to a memory-bound runtime. Stemming from the gap between processor and memory speed, this bottleneck can be alleviated through alternative computing architectures. Recent FPGA devices, equipped with on-chip High-Bandwidth Memory (HBM), enable custom architectures to employ high-capacity, high-bandwidth memory to address memory-bound tasks. This research investigates accelerating k-mers counting with one such device, the BittWare 520N-MX, a Stratix 10 FPGA with 16 GB of on-chip HBM2. The architecture was designed using Intel’s oneAPI framework. The accelerator architecture leverages inherent parallelism in the algorithm via multiple parallel hash functions, along with partitioning data structures across multiple memory banks, and employing multiple independent parallel processing pipelines on the device to maximize throughput. The accelerator achieves 57.98M k-mers per second, 3.80× more than the throughput-optimized CPU version and 5.85× more than the original CPU app. This was done despite the clock speeds in the oneAPI design falling well below the board’s maximum frequency. Multiple methods of improving the clock speeds were attempted but were ultimately unsuccessful. OneAPI was able to achieve speedup over the CPU using the FPGA equipped with the on-chip HBM2, but there is the potential for additional performance improvement with higher FPGA clock speeds.
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Details
| Item Type: |
University of Pittsburgh ETD
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| Status: |
Unpublished |
| Creators/Authors: |
| Creators | Email | Pitt Username | ORCID  |
|---|
| Lucas, Owen | | | |
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| ETD Committee: |
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| Date: |
6 September 2024 |
| Date Type: |
Publication |
| Defense Date: |
30 July 2024 |
| Approval Date: |
6 September 2024 |
| Submission Date: |
25 June 2024 |
| Access Restriction: |
No restriction; Release the ETD for access worldwide immediately. |
| Number of Pages: |
61 |
| Institution: |
University of Pittsburgh |
| Schools and Programs: |
Swanson School of Engineering > Electrical and Computer Engineering |
| Degree: |
MS - Master of Science |
| Thesis Type: |
Master's Thesis |
| Refereed: |
Yes |
| Uncontrolled Keywords: |
Field programmable gate arrays, bioinformatics, high level synthesis, hardware acceleration, design tools, memory management, reconfigurable architectures |
| Date Deposited: |
06 Sep 2024 19:56 |
| Last Modified: |
06 Sep 2024 19:56 |
| URI: |
http://d-scholarship.pitt.edu/id/eprint/46625 |
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