Zhao, Bo
(2010)
Variation-Tolerant Non-Uniform 3D Cache Management in Memory Stacked Multi-Core Processors.
Master's Thesis, University of Pittsburgh.
(Unpublished)
Abstract
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures such as DRAMs. DRAMs are built using minimized transistors with presumably uniform speed in an organized array structure. Process variation can introduce latency disparity among different memory arrays. With the proliferation of 3D stacking technology, DRAMs become a favorable choice for stacking on top of a multi-core processor as a last level cache for large capacity, high bandwidth, and low power. Hence, variations in bank speed create a unique problem of non-uniform cache accesses in the 3D space.In this thesis, we investigate cache management techniques for tolerating process variation in a 3D DRAM stacked onto a multi-core processor. We modeled the process variation in a 4-layer DRAM memory to characterize the latency variations among different banks. As a result, the notion of fast and slow banks from the core's standpoint is no longer associated with their physical distances with the banks. They are determined by the different bank latencies due to process variation. We develop cache migration schemes that utilize fast banks while limiting the cost due to migration. Our experiments show that there is a great performance benefit in exploiting fast memory banks through migration. On average, a variation-aware management can improve the performance of a workload over the baseline (where the speed of the slowest bank is assumed for all banks) by 17.8%. We are also only 0.45% away in performance from an ideal memory where no PV is present.
Share
| Citation/Export: |
|
| Social Networking: |
|
Details
| Item Type: |
University of Pittsburgh ETD
|
| Status: |
Unpublished |
| Creators/Authors: |
|
| ETD Committee: |
|
| Date: |
26 January 2010 |
| Date Type: |
Completion |
| Defense Date: |
26 June 2009 |
| Approval Date: |
26 January 2010 |
| Submission Date: |
3 July 2009 |
| Access Restriction: |
No restriction; Release the ETD for access worldwide immediately. |
| Institution: |
University of Pittsburgh |
| Schools and Programs: |
Swanson School of Engineering > Electrical Engineering |
| Degree: |
MSEE - Master of Science in Electrical Engineering |
| Thesis Type: |
Master's Thesis |
| Refereed: |
Yes |
| Uncontrolled Keywords: |
3D Die Stacking; DRAM; Last-Level Cache; Non-Uniform Cache Architecture (NUCA); Process Variation |
| Other ID: |
http://etd.library.pitt.edu/ETD/available/etd-07032009-225329/, etd-07032009-225329 |
| Date Deposited: |
10 Nov 2011 19:49 |
| Last Modified: |
15 Nov 2016 13:45 |
| URI: |
http://d-scholarship.pitt.edu/id/eprint/8259 |
Metrics
Monthly Views for the past 3 years
Plum Analytics
Actions (login required)
 |
View Item |
![[feed]](/images/feed-icon-32x32.png){kind=icon}