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Accelerating Regular-Expression Matching on FPGAs with High-Level Synthesis

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43 pages

Title
  • Accelerating Regular-Expression Matching on FPGAs with High-Level Synthesis
Date modified
  • 08/21/2025
Creator
Abstract
  • The importance of security infrastructures for high-throughput networks has rapidly grown as a result of expanding internet traffic and increasingly high-bandwidth connections. Intrusion-detection systems (IDSs), such as SNORT, rely upon rule sets designed to alert system administrators of malicious packets. Methods for deep-packet inspection, which often depend upon regular-expression searches, can be accelerated on programmable-logic (PL) architectures using non-deterministic finite automata (NFAs). Prior designs have relied upon register-transfer level (RTL) design descriptions and have achieved efficient resource utilization through fine-grained optimizations. New advances made by field-programmable gate array (FPGA) vendors have led to powerful compiler toolchains for OpenCL and SYCL that allow for rapid development on PL architectures while generating competitive designs in terms of performance. The goal of this research is to evaluate performance differences between a custom, SYCL- and OpenCL-based, acceleration architecture for regular expressions and comparable RTL-based designs. The simplicity of the application, which requires only basic hardware building blocks, adds to the novelty of the comparison. In contrast to prior RTL-based solutions, which show frequency degradation with bandwidth scaling, this approach is able to maintain stable and high operating frequencies at the cost of resource usage. By scaling input bandwidth with multi-character transformations, high-throughput designs can be realized.Using Intel's OpenCL compiler, throughputs in excess of 17 Gbps can be achieved on Intel’s Arria 10 Programmable Acceleration Card and 19.4 Gbps with Intel's Stratix 10 Programmable Acceleration Card, outperforming similar designs with RTL, as reported in the literature. SYCL-based designs, synthesized with Intel's oneAPI compiler show performance degradation but still achieve higher throughput, up to 15.6 Gbps, than past RTL-based implementations. Overall, OpenCL and SYCL development yields both competitive results, when compared to the fine-grained RTL development process, and many ease-of-use improvements and design abstractions.
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Date created
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Language
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Degree discipline
  • Electrical and Computer Engineering
Degree grantor
  • University of Pittsburgh
Degree level
  • Masters
Degree name
  • Master of Science in Computer Engineering
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MLA citation style (9th ed.)

Callanan, Devon. Accelerating Regular-expression Matching On Fpgas with High-level Synthesis. . 2021. d-scholarship.pitt.edu/concern/etds/d3067db2-d4f0-49c5-8937-a705eaa891ac.

APA citation style (7th ed.)

C. Devon. (2021). Accelerating Regular-Expression Matching on FPGAs with High-Level Synthesis. https://d-scholarship.pitt.edu/concern/etds/d3067db2-d4f0-49c5-8937-a705eaa891ac

Chicago citation style (CMOS 17, author-date)

Callanan, Devon. Accelerating Regular-Expression Matching On Fpgas with High-Level Synthesis. 2021. https://d-scholarship.pitt.edu/concern/etds/d3067db2-d4f0-49c5-8937-a705eaa891ac.

Note: These citations are programmatically generated and may be incomplete.

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