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Cache Side Channel Attacks on Modern Processors

Guo, Yanan (2024) Cache Side Channel Attacks on Modern Processors. Doctoral Dissertation, University of Pittsburgh. (Unpublished)

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Abstract

Modern CPUs feature many microarchitectural structures shared among users. Although such resource sharing offers performance benefits, it also creates opportunities for side channel attacks. Attackers capable of manipulating microarchitectural states can bring these structures into specific states, and then monitor any unintended state changes induced by the victim. Cache timing covert channels and side channel attacks, or cache attacks for short, are extremely potent. Attackers can exploit changes in cache states to leak sensitive information from another user. For performance and efficiency purposes, modern CPUs often include instructions and designs that allow users to directly influence cache states. This inadvertently makes it easier for attackers to manipulate these states, potentially resulting in new and more efficient cache attacks. This dissertation analyzes how these instructions and designs can be exploited for powerful cache attacks and develops mitigation strategies against these attacks.

First, we reverse engineer the prefetch-for-write instruction (PREFETCHW) on Intel CPUs and uncover a severe vulnerability on them. Based on this vulnerability, we develop two new cache attacks. These attacks significantly outperform arguably the most prevalent cache attack, Flush+Reload, in both bandwidth and temporal resolution.

Second, we study the non-temporal prefetch instruction (PREFETCHNTA) on Intel processors and uncover its unique behavior within the cache hierarchy. This behavior enables a fast route to trigger cache conflicts. We demonstrate that applying this instruction in conflict-based cache attacks can significantly improve the attack performance.

Third, the CPU uncore has been a frequent target for side channel attacks, as it is shared among all users. Many studies suggest using uncore resource partitioning as a countermeasure, given that most uncore attacks stem from resource contention. However, we show that such partitioning is not foolproof. Specifically, we reverse engineer the details of the uncore frequency scaling technique on Intel processors and discover that this technique creates a robust side channel that cannot be stopped by traditional defense designs based on partitioning.

Finally, we study the potential countermeasures against these new attacks and propose defense mechanisms to mitigate each of these attacks with minimal impact on performance.


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Details

Item Type: University of Pittsburgh ETD
Status: Unpublished
Creators/Authors:
CreatorsEmailPitt UsernameORCID
Guo, Yananyag45@pitt.eduyag450000-0003-0034-0358
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairYang, Junjuy9@pitt.edu
Committee MemberZhou, Peipeipeipei.zhou@pitt.edu
Committee MemberHu, Jingtongjthu@pitt.edu
Committee MemberDickerson, Samueldickerson@pitt.edu
Committee MemberZhang, Youtaozhangyt@cs.pitt.edu
Committee MemberXiong, Wenjiewenjiex@vt.edu
Date: 6 September 2024
Date Type: Publication
Defense Date: 31 May 2024
Approval Date: 6 September 2024
Submission Date: 18 June 2024
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Number of Pages: 148
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical and Computer Engineering
Degree: PhD - Doctor of Philosophy
Thesis Type: Doctoral Dissertation
Refereed: Yes
Uncontrolled Keywords: hardware security, cache, side channels
Date Deposited: 06 Sep 2024 19:55
Last Modified: 06 Sep 2024 19:55
URI: http://d-scholarship.pitt.edu/id/eprint/46577

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