Sun, Zhenyu
(2014)
High-Performance and Low-Power Magnetic Material Memory Based Cache Design.
Doctoral Dissertation, University of Pittsburgh.
(Unpublished)
Abstract
Magnetic memory technologies are very promising candidates to be universal memory due to its good scalability, zero standby power and radiation hardness. Having a cell area much smaller than SRAM, magnetic memory can be used to construct much larger cache with the same die footprint, leading to siginficant improvement of overall system performance and power consumption especially in this multi-core era. However, magnetic memories have their own drawbacks such as slow write, read disturbance and scaling limitation, making its usage as caches challenging.
This dissertation comprehensively studied these two most popular magnetic memory technologies. Design exploration and optimization for the cache design from different design
layers including the memory devices, peripheral circuit, memory array structure and micro-architecture are presented. By leveraging device features, two major micro-architectures -multi-retention cache hierarchy and process-variation-aware cache are presented to improve the write performance of STT-RAM. The enhancement in write performance results in the
degradation of read operations, in terms of both speed and data reliability. This dissertation also presents an architecture to resolve STT-RAM read disturbance issue. Furthermore, the scaling of STT-RAM is hindered due to the required size of switching transistor. To break the cell area limitation of STT-RAM, racetrack memory is studied to achieve an even higher memory density and better performance and lower energy consumption. With dedicated elaboration, racetrack memory based cache design can achieve a siginificant area reduction and energy saving when compared to optimized STT-RAM.
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Details
| Item Type: |
University of Pittsburgh ETD
|
| Status: |
Unpublished |
| Creators/Authors: |
|
| ETD Committee: |
|
| Date: |
29 January 2014 |
| Date Type: |
Publication |
| Defense Date: |
15 December 2013 |
| Approval Date: |
29 January 2014 |
| Submission Date: |
21 November 2013 |
| Access Restriction: |
No restriction; Release the ETD for access worldwide immediately. |
| Number of Pages: |
177 |
| Institution: |
University of Pittsburgh |
| Schools and Programs: |
Swanson School of Engineering > Electrical Engineering |
| Degree: |
PhD - Doctor of Philosophy |
| Thesis Type: |
Doctoral Dissertation |
| Refereed: |
Yes |
| Uncontrolled Keywords: |
MRAM, STT-RAM, racetrack memory, retention time, process variation, read disturbance, cross layer, resizable cache |
| Date Deposited: |
29 Jan 2014 18:32 |
| Last Modified: |
15 Nov 2016 14:15 |
| URI: |
http://d-scholarship.pitt.edu/id/eprint/20043 |
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