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A 64-WAY HYPERCUBE INTERCONNECTED SINGLE INSTRUCTION, MULTIPLE DATA ARCHITECTURE FOR FIELD PROGRAMMABLE GATE ARRAYS

Werger, Katrina Jean-Marie (2004) A 64-WAY HYPERCUBE INTERCONNECTED SINGLE INSTRUCTION, MULTIPLE DATA ARCHITECTURE FOR FIELD PROGRAMMABLE GATE ARRAYS. Master's Thesis, University of Pittsburgh. (Unpublished)

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Abstract

The architecture of modern FPGAs contain over one thousand 512-bit memory banks, over five hundred 4k-bit memory banks, and over one hundred thousand logic elements. This inherent parallelism of an FPGA makes it an ideal platform for a multiprocessor architecture. In addition to embedded memory, hundreds of ASIC multipliers are embedded into modern FPGA architectures. This thesis introduces three Single-Instruction-Multiple-Data architectures comprised of 2, 4, 8, 16, 32, 64 and 88 processing elements. The first architecture uses configurable logic to implement the processing elements while second and third architectures are built around ASIC multipliers and use configurable logic to implement customizable instruction. All of the architectures described in this thesis are controlled by a central instruction stream. The 64 interconnected processor SIMD design operates at 94 MHz, and utilizes 73% of the DSP blocks available in the Altera Stratix EPS80F1508C6 device but only 24% of the look-up table logic. The remaining 76% of the logic cells are available for custom instructions.


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Details

Item Type: University of Pittsburgh ETD
Status: Unpublished
Creators/Authors:
CreatorsEmailPitt UsernameORCID
Werger, Katrina Jean-Mariekjw_9@yahoo.com
ETD Committee:
TitleMemberEmail AddressPitt UsernameORCID
Committee ChairHoare, Raymond Rhoare@pitt.eduHOARE
Committee MemberJones, Alex Kakjones@engr.pitt.eduAKJONES
Committee MemberLevine, Benjaminblevine@engr.pitt.edu
Committee MemberMickle, Marlin Hmickle@ee.pitt.eduMICKLE
Date: 2 February 2004
Date Type: Completion
Defense Date: 25 November 2003
Approval Date: 2 February 2004
Submission Date: 2 December 2003
Access Restriction: No restriction; Release the ETD for access worldwide immediately.
Institution: University of Pittsburgh
Schools and Programs: Swanson School of Engineering > Electrical Engineering
Degree: MSEE - Master of Science in Electrical Engineering
Thesis Type: Master's Thesis
Refereed: Yes
Uncontrolled Keywords: Parallel Processing; FPGA; SIMD
Other ID: http://etd.library.pitt.edu/ETD/available/etd-12022003-121419/, etd-12022003-121419
Date Deposited: 10 Nov 2011 20:07
Last Modified: 19 Dec 2016 14:37
URI: http://d-scholarship.pitt.edu/id/eprint/9939

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